Tri-gate devices and methods of fabrication

• US 7,504,678 B2
• Filed: 11/07/2003
• Issued: 03/17/2009
• Est. Priority Date: 08/23/2002
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Barlage, Douglas, Chau, Robert S., Kavalieros, Jack, Doyle, Brian S., Datta, Suman
• Primary Examiner(s): Doan; Theresa T
• Application Number:
  US10/703,316
• Publication Number:
  US 20040094807A1
• Time in Patent Office: 1,957 Days
• Field of Search: 438/149, 438/176, 438/197, 438/283, 438/304, 257287-288, 257329-332, 257/347, 257/401, 257/60
• US Class Current: 257/287
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/482 the IGFET comprising multiple separately-addressable gate electrodes
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/842 for carbon nanotubes or fullerenes
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Claims

1. A tri-gate transistor comprising:

a single crystalline silicon body on a substrate, said single crystalline silicon body having a top surface and a pair of laterally opposite sidewalls;

a continuous gate dielectric formed on said top surface of said single crystalline silicon body and on said laterally opposite sidewalls of said single crystalline silicon body;

a gate electrode formed on said gate dielectric on said top surface of said single crystalline silicon body and adjacent to said gate dielectric on said laterally opposite sidewalls of said single crystalline silicon body, said gate electrode having a pair of laterally opposite sidewalls separated by a first distance that run perpendicular to the laterally opposite sidewalls of the semiconductor body, and wherein the gate electrode provides a first gate adjacent to the top surface of the single crystalline silicon body, a second gate adjacent to one of the laterally opposite sidewalls of the single crystalline silicon body, and a third gate adjacent to the other of the laterally opposite sidewalls of the single crystalline silicon body; and

a pair of source/drain regions formed in said single crystalline silicon body on opposite sides of said gate electrode wherein a channel region is located between said pair of source/drain regions and beneath said gate electrode, wherein said channel region has a first concentration of a first conductivity type and wherein said channel region has a doped region of a second concentration of said first conductivity type said second concentration greater than said first concentration.

2. The tri-gate transistor of claim 1 wherein said first concentration between 1×

10¹⁶-1×

10²⁰ atoms/cm³.

3. The tri-gate transistor of claim 2 wherein said first concentration is between 1×

10¹⁶-1×

10¹⁸ atoms/cm³.

4. The tri-gate transistor of claim 1 further comprising a pair of sidewall spacer formed along laterally opposite sidewalls of said gate electrode.

5. The tri-gate transistor of claim 1 wherein said pair of source/drain regions further comprise silicon formed on and around said silicon body.

6. The tri-gate transistor of claim 5 wherein said silicon on said source/drain regions is epitaxial silicon.

7. A transistor comprising:

a first semiconductor body and a second semiconductor body, each semiconductor body having a top surface opposite a bottom surface formed on a substrate and a pair of laterally opposite sidewalls and an insulating layer located between the first and second semiconductor bodies;

a first continuous gate dielectric formed on the top surface and sidewalls of the first semiconductor body and a second continuous gate dielectric formed on the top surface and sidewalls of the second semiconductor body;

a gate electrode formed on the gate dielectrics on the top surface of said semiconductor bodies and adjacent to said gate dielectrics formed on the laterally opposite sidewalls of said semiconductor bodies and above said insulating layer between said plurality of semiconductor bodies, wherein the gate electrode provides a pair of first gates adjacent to the top surface of each of the semiconductor bodies, a second pair of gates adjacent to one of the laterally opposite sidewalls of each of the semiconductor bodies, and a third pair of gates adjacent to the other of the laterally opposite sidewalls of each of the semiconductor bodies;

a first source region and a first drain region in said first semiconductor body on opposite sides of said gate electrode;

a second source region and a second drain region in said second semiconductor body on opposite sides of said gate electrode;

a source landing pad which connects said first source region and said second source region; and

a drain landing pad which connects said first drain region and said second drain region.

8. The transistor of claim 7 wherein the distance between the laterally opposite sidewalls of the first and second semiconductor bodies is approximately the same.

9. The transistor of claim 7 wherein each of said source regions are coupled together and each of said drain regions are coupled together.

10. The transistor of claim 7 wherein said substrate is an insulating substrate.

11. The transistor of claim 7 wherein said substrate is a semiconductor substrate.

12. A semiconductor device comprising:

a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

a continuous gate dielectric layer on said top surface and on said laterally opposite sidewalls of said semiconductor body;

a gate electrode on said gate dielectric layer and adjacent to said gate dielectric layer on said laterally opposite sidewalls of said semiconductor body, the gate electrode having laterally opposite sidewalls that run perpendicular to the laterally opposite sidewalls of the semiconductor body, and wherein the gate electrode provides a first gate adjacent to the top surface of the semiconductor body, a second gate adjacent to one of the laterally opposite sidewalls of the semiconductor body, and a third gate adjacent to the other of the laterally opposite sidewalls of the semiconductor body;

a pair of source/drain extensions in said semiconductor body on opposite sides of said gate electrode;

a pair of sidewall spacers on opposite sides of said laterally opposite sidewalls of said gate electrode on said source/drain extensions in said semiconductor body;

a pair of source/drain contact regions in said semiconductor body adjacent to said sidewall spacers; and

a semiconductor film on and around said semiconductor body adjacent to said sidewall spacer.

13. The device of claim 12 wherein said semiconductor film is silicon and said semiconductor body is silicon.

14. The device of claim 13 further comprising silicide on said silicon film formed on said silicon body.

15. A transistor comprising:

a semiconductor body having a top surface and laterally opposite sidewalls on a substrate;

a continuous gate dielectric layer on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body;

a gate electrode on said gate dielectric layer on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body, the gate electrode having laterally opposite sidewalls that run perpendicular to the laterally opposite sidewalls of the semiconductor body, and wherein the gate electrode provides a first gate adjacent to the top surface of the semiconductor body, a second gate adjacent to one of the laterally opposite sidewalls of the semiconductor body, and a third gate adjacent to the other of the laterally opposite sidewalls of the semiconductor body;

a pair of sidewalls spacers on opposite sides of said laterally opposite sidewalls on said gate electrode;

a semiconductor film on the top surface of said semiconductor body and on said opposite sidewalls of said semiconductor body and adjacent to said pair of sidewalls spacer; and

a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode.

16. The transistor of claim 15 further comprising a halo region in said semiconductor body beneath said gate electrode.

17. The transistor of claim 15 wherein said gate electrode has a height of at least 3 times a height of said semiconductor body.

18. The transistor of claim 15 further comprising a refractory metal silicide on said semiconductor film on said top surface and on said laterally opposite sidewalls of said semiconductor body.

19. A nonplanar transistor comprising:

a semiconductor body having a first concentration of a first conductivity type dopant on a substrate, said semiconductor body having a top surface and a pair of laterally opposite sidewalls;

a continuous gate dielectric layer on said pair of laterally opposite sidewalls of said semiconductor body;

a gate electrode on said gate dielectric layer on said top surface of said semiconductor body and adjacent to said pair of laterally opposite sidewalls, the gate electrode having laterally opposite sidewalls that run perpendicular to the laterally opposite sidewalls of the semiconductor body, and wherein the gate electrode provides a first gate adjacent to the top surface of the semiconductor body, a second gate adjacent to one of the laterally opposite sidewalls of the semiconductor body, and a third gate adjacent to the other of the laterally opposite sidewalls of the semiconductor body, and wherein a channel is formed in said semiconductor body beneath said gate electrode;

a doped region having a second concentration of said first conductivity type in said channel region of said semiconductor body wherein said second concentration is greater than said first concentration;

a pair of source/drain region in said semiconductor body on opposite sides of said gate electrode;

a pair of sidewall spacers on opposite sides of the laterally opposite sidewalls of the gate electrode; and

a semiconductor film on the top surface and on said laterally opposite sidewalls of said semiconductor body on opposite sides of said gate electrode and adjacent to said pair of sidewalls spacers.