Parallel data processing apparatus

• US 7,506,136 B2
• Filed: 01/10/2007
• Issued: 03/17/2009
• Est. Priority Date: 04/09/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Clearspeed Technology PLC (ZF Acquisitions Ltd.)
• Inventors: David, Russell, McConnell, Ray, Rhoades, John, Cameron, Ken, Winser, Paul, Faulds, Gordon, Greer, Trey, Atkin, Phil, Stuttard, Dave, Day, Tim, Williams, Dave, O'Dea, Eamon
• Primary Examiner(s): Treat; William M
• Application Number:
  US11/621,952
• Publication Number:
  US 20070245132A1
• Time in Patent Office: 797 Days
• Field of Search: 345501-506, 345/519, 345/522, 712/20, 712/22
• US Class Current: 712/22
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A controller for controlling a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, comprises a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another, and a distribution unit operable to supply such incoming instruction streams to respective ones of the said plurality of processor arrays.

Claims

1. A controller for controlling a data processor having a plurality of SIMD (single instruction multiple data) processor arrays, each of which includes a plurality of processing elements, the controller comprising:

a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another; and

a distribution unit operable to supply such incoming instruction streams to respective ones of the said plurality of processor arrays, wherein the distribution unit is operable to distribute the instruction streams to a plurality of first function controllers operable to control the processing elements in respective processor arrays, and to a plurality of second function controllers operable to control input/output functions of respective arrays of processing elements, the first and second function controllers operating asynchronously.

2. A controller as claimed in claim 1, comprising a cache memory for storing retrieved instruction streams.

3. A controller as claimed in claim 1, comprising a first-in-first-out buffer for storing retrieved instruction streams.

4. A controller as claimed in claim 1, comprising a synchronization controller for controlling synchronization between instruction streams.

5. A controller as claimed in claim 1, comprising a synchronization unit for controlling synchronization between instruction streams and external hardware units.

6. A controller as claimed in claim 1, comprising a synchronization unit for controlling synchronization between instruction streams and other control units of the array.

7. A controller as claimed in claim 1, comprising a synchronization unit for controlling synchronization between instruction streams and events external to the instruction streams.

8. A controller as claimed in claim 1, comprising a synchronization unit for controlling synchronization of the instruction streams using semaphore status indicators.

9. A controller as claimed in claim 1, wherein the controller is operable to stall an instruction stream when a functional unit external to the array of processing elements is unavailable.

10. A controller as claimed in claim 1, wherein the controller is operable to stall an instruction stream when a functional unit external to the array of processing elements is unavailable, and to restart a stalled instruction stream when the functional unit is available.

11. A controller as claimed in claim 1, comprising:

an instruction stream processor for controlling a plurality of instruction streams;

a synchronization controller for controlling synchronization between instruction streams;

a status block for providing status information regarding each of the instruction streams; and

a scheduling means connected to receive status information, and operable to determine which of the instruction streams is to be active.

12. A controller as claimed in claim 1, wherein the controller is operable to assign each instruction stream a relative priority level.

13. A controller as claimed in claim 1, comprising a scheduler connected to receive status information from functional units external to the array of processing elements, and operable to schedule instruction streams using such received status information.

14. A data processor comprising a plurality of SIMD (single instruction multiple data) processor arrays, each of which includes a plurality of processing elements, and a controller, wherein the controller comprises:

a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another; and

a distribution unit operable to supply such incoming instruction streams to respective ones of the said plurality of processor arrays, wherein the distribution unit is operable to distribute the instruction streams to a plurality of first function controllers operable to control the processing elements in respective processor arrays, and to a plurality of second function controllers operable to control input/output functions of respective arrays of processing elements, the first and second function controllers operating asynchronously.

15. A data processor as claimed in claim 14, wherein the controller comprises a cache memory for storing retrieved instruction streams.

16. A data processor as claimed in claim 14, wherein the controller comprises a first-in-first-out buffer for storing retrieved instruction streams.

17. A data processor as claimed in claim 14, wherein the controller comprises a synchronization unit for controlling synchronization between instruction streams.

18. A data processor as claimed in claim 14, wherein the controller comprises a synchronization unit for controlling synchronization between instruction streams and external hardware units.

19. A data processor as claimed in claim 14, comprising a synchronization unit for controlling synchronization between instruction streams and other control units of the array.

20. A data processor as claimed in claim 14, comprising a synchronization unit for controlling synchronization between instruction streams and events external to the instruction streams.

21. A data processor as claimed in claim 14, comprising a synchronization unit for controlling synchronization of the instruction streams using semaphore status indicators.

22. A data processor as claimed in claim 14, wherein the controller is operable to stall an instruction stream when a functional unit external to the array of processing elements is unavailable.

23. A data processor as claimed in claim 14, wherein the controller is operable to stall an instruction stream when a functional unit external to the array of processing elements is unavailable, and to restart a stalled instruction stream when the functional unit is available.

24. A data processor as claimed in claim 14, wherein the controller comprises:

an instruction stream processor for controlling a plurality of instruction streams;

a synchronization controller for controlling synchronization between instruction streams;

a status block for providing status information regarding each of the instruction streams; and

a scheduling means connected to receive status information, and operable to determine which of the instruction streams is to be active.

25. A data processor as claimed in claim 14, wherein the controller is operable to assign each instruction stream a relative priority level.

26. A data processor as claimed in claim 14, wherein the controller comprises a scheduler connected to receive status information from functional units external to the array of processing elements, and operable to schedule instruction streams using such received status information.

27. A method for controlling a data processor having a plurality of SIMD (single instruction multiple data) processor arrays, each of which includes a plurality of processing elements, the method comprising receiving a plurality of incoming instruction streams in parallel, and supplying such incoming instructions streams to respective ones of the said plurality of processor arrays, comprising distributing the instruction streams to a plurality of first function controllers operable to control the processing elements in respective processor arrays, and to a plurality of second function controllers operable to control input/output functions of respective arrays of processing elements, the first and second function controllers operating asynchronously.

28. A method as claimed in claim 27 comprising storing retrieved instruction streams in a cache memory.

29. A method as claimed in claim 27 comprising storing retrieved instruction streams in a first-in-first-out buffer.

30. A method as claimed in claim 27 comprising controlling synchronization between instruction streams.

31. A method as claimed in claim 27 comprising controlling synchronization between instruction streams and external hardware units.

32. A method as claimed in claim 27 comprising controlling synchronization between instruction streams and other control units of the array.

33. A method as claimed in claim 27, comprising controlling synchronization between instruction streams and events external to the instruction streams.

34. A method as claimed in claim 27, comprising controlling synchronization of the instruction streams using semaphore status indicators.

35. A method as claimed in claim 27, stalling an instruction stream when a functional unit external to the array of processing elements is unavailable.

36. A method as claimed in claim 27, stalling an instruction stream when a functional unit external to the array of processing elements is unavailable, and restarting a stalled instruction stream when the functional unit is available.

37. A method as claimed in claim 27, comprising:

controlling a plurality of instruction streams;

controlling synchronization between instruction streams;

providing status information regarding each of the instruction streams; and

receiving status information, and determining which of the instruction streams is to be active.

38. A method as claimed in claim 27, comprising assigning each instruction stream a relative priority level.

39. A controller as claimed in claim 27, comprising receiving status information from functional units external to the array of processing elements, and scheduling instruction streams using such received status information.