Robust index storage for non-volatile memory

• US 7,509,474 B2
• Filed: 06/08/2005
• Issued: 03/24/2009
• Est. Priority Date: 06/08/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wong, Wanmo
• Primary Examiner(s): Ellis; Kevin L
• Assistant Examiner(s): Farrokh; Hashem
• Application Number:
  US11/148,028
• Publication Number:
  US 20060282644A1
• Time in Patent Office: 1,385 Days
• Field of Search: 711/103, 711/206
• US Class Current: 711/206
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation.

Claims

1. A method of operating a non-volatile memory device, comprising:

looking up a logical sector address of a memory access to the non-volatile memory in a hierarchal address translation data structure to translate the logical sector address to a physical sector address, wherein the hierarchal address translation data structure contains two or more Tables/data structures arranged in a hierarchal data tree;

accessing the logical sector address in a physical sector address of the memory array in reference to a version number stored in a version number data field of the sector; and

accessing the physical sector address in the non-volatile memory device.

2. The method of claim 1, wherein the hierarchal address translation data structure further comprises:

a Root Table;

one or more Child Tables; and

wherein the Root Table contains one or more address pointer data entries to the one or more Child Tables, and each of the one or more Child Tables contain one or more address translation data entries to translate a logical address to a physical address.

3. The method of claim 2, wherein each of the Root Table'"'"'s one or more address pointers data entries to the one or more Child Tables can be updated one or more times without overwriting the previous pointer data stored in the entry, and each of the one or more Child Table'"'"'s one or more address translation data entries can be updated one or more times without overwriting the previous translation data stored in the entry.

4. The method of claim 2, further comprising an Entry Point data structure, wherein the Entry Point data structure contains an address pointer data entry to the Root Table.

5. The method of claim 4, wherein the Entry Point data structure'"'"'s address pointer data entry to the Root Table can be updated one or more times without overwriting the previous pointer data stored in the entry.

6. The method of claim 1, wherein looking up a logical address of a memory access to the non-volatile memory in a hierarchal address translation data structure further comprises:

traversing the hierarchal data tree of the hierarchal address translation data structure starting from a Root Table;

selecting a Child Table containing an address translation data entry for the accessed logical address; and

reading the address translation data entry for the accessed logical address to translate the logical address to a physical address.

7. The method of claim 6, wherein traversing the hierarchal data tree of the hierarchal address translation data structure starting from a Root Table further comprises retrieving the address to the Root Table from an Entry Point data structure.

8. The method of claim 1, wherein the hierarchal address translation data structure further comprises a Logical to Physical Erase Block Translation Table.

9. The method of claim 8, further comprising:

translating a logical erase block ID to a physical erase block ID utilizing the Logical to Physical Erase Block Translation Table.

10. The method of claim 1, wherein looking up a logical address of a memory access to the non-volatile memory in a hierarchal address translation data structure to translate the logical sector address to a physical sector address further comprises looking up a logical address of a memory access to the non-volatile memory in a hierarchal address translation data structure to translate the logical sector address to a physical cluster address, wherein each cluster contains one or more consecutively addressed sectors.

11. The method of claim 1, wherein an Entry Point is stored at a known address location or is stored within a defined Control Area of the non-volatile memory device.

12. The method of claim 11, wherein the Entry Point stores one of configuration information or a pointer to configuration information for the non-volatile memory device.

13. A method of operating a non-volatile memory device, comprising:

looking up a logical sector address of a memory access to the non-volatile memory in a hierarchal address translation data structure to translate the logical sector address to a physical sector address, wherein the hierarchal address translation data structure contains two or more Tables/data structures arranged in a hierarchal data tree;

accessing the physical sector address in the non-volatile memory device;

updating the hierarchal address translation data structure when user data stored in the non-volatile memory device is updated by traversing up the hierarchal address translation data structure, starting with a Table storing the changed address translation entry, the updating further comprising;

checking if update space remains in a changed data entry or address pointer data entry in a current Table/data structure of a current level of the hierarchal address translation data structure;

updating the changed data entry or address pointer data entry when update space is available, and ending the update of the hierarchal address translation data structure;

creating a new Table/data structure when the changed data entry cannot be updated in the current Table/data structure;

copying the most-current entries/pointers to the new Table/data structure;

ending the update of the hierarchal address translation data structure if the current Table/data structure is at a top level of the hierarchal address translation data structure;

traversing up to a next level of the hierarchal address translation data structure if the current Table/data structure is not at the top level of the hierarchal address translation data structure; and

repeating updating on a parent Table/data structure of the next level to change an address pointer in the parent Table/data structure from the current to the new Table/data structure.

14. A method of storing address translation data in a non-volatile memory array, comprising:

storing address translation data in a hierarchal address translation data structure of two or more Tables/data structures, where the two or more Tables/data structures are arranged in a hierarchal tree; and

updating the hierarchal address translation data structure when user data stored in the non-volatile memory array is updated by traversing up the hierarchal address translation data structure, starting with a Table storing the changed address translation entry, the updating further comprising;

checking if update space remains in a changed data entry or address pointer data entry in a current Table/data structure of a current level of the hierarchal address translation data structure;

updating the changed data entry or address pointer data entry when update space is available, and ending the update of the hierarchal address translation data structure;

creating a new Table/data structure when the changed data entry cannot be updated in the current Table/data structure;

copying the most-current entries/pointers to the new Table/data structure;

ending the update of the hierarchal address translation data structure if the current Table/data structure is at a top level of the hierarchal address translation data structure;

traversing up to a next level of the hierarchal address translation data structure if the current Table/data structure is not at the top level of the hierarchal address translation data structure; and

repeating updating on a parent Table/data structure of the next level to change an address pointer in the parent Table/data structure from the current to the new Table/data structure.

15. The method of claim 14, wherein the hierarchal address translation data structure further comprises:

a Root Table;

one or more Child Tables; and

wherein the Root Table contains one or more address pointer data entries to the one or more Child Tables, and each of the one or more Child Tables contain one or more address translation data entries to translate a logical address to a physical address.

16. The method of claim 15, wherein each of the Root Table'"'"'s one or more address pointers data entries to the one or more Child Tables can be updated one or more times without overwriting the previous pointer data stored in the entry, and each of the one or more Child Table'"'"'s one or more address translation data entries can be updated one or more times without overwriting the previous translation data stored in the entry.

17. The method of claim 15, further comprising an Entry Point data structure, wherein the Entry Point data structure contains an address pointer data entry to the Root Table.

18. The method of claim 17, wherein the Entry Point data structure'"'"'s address pointer data entry to the Root Table can be updated one or more times without overwriting the previous pointer data stored in the entry.

19. A non-volatile memory device, comprising:

a non-volatile memory array having a plurality of non-volatile memory cells; and

a control circuit, wherein the control circuit is adapted to access a logical address from the memory array by translating the logical address to a physical sector address of the memory array in reference to a hierarchal address translation data structure stored in the non-volatile memory array, wherein the hierarchal address translation data structure comprises;

an Entry Point;

a Root Table;

one or more Child Tables; and

wherein the Entry Point contains an address pointer data entry to the Root Table, the Root Table contains one or more address pointer data entries to the one or more Child Tables, and each of the one or more Child Tables contain one or more address translation data entries to translate a logical address to a physical address; and

wherein the control circuit is further adapted to update the hierarchal address translation data structure when user data stored in the non-volatile memory array is updated by traversing up the hierarchal address translation data structure, starting with the Child Table storing the changed address translation entry, updating the hierarchal address translation data structure further comprising;

checking if update space remains in a changed data entry or address pointer data entry in a current Table/data structure of a current level of the hierarchal address translation data structure;

updating the changed data entry or address pointer data entry when update space is available, and ending the update of the hierarchal address translation data structure;

creating a new Table/data structure when the changed data entry cannot be updated in the current Table/data structure;

copying the most-current entries/pointers to the new Table/data structure;

ending the update of the hierarchal address translation data structure if the current Table/data structure is the Entry Point;

traversing up to a next level of the hierarchal address translation data structure if the current Table/data structure is not the Entry Point; and

repeating updating on a parent Table/data structure of the next level to change an address pointer in the parent Table/data structure from the current to the new Table/data structure.

20. The non-volatile memory device of claim 19, wherein the one or more Child Tables are arranged in one or more layers of Tables, where each of the one or more Child Tables in a bottom layer of Child Tables contain one or more address translation data entries to translate a logical address to a physical address and each of the one or more Child Tables in intervening layers of Child Tables contain one or more address pointer data entries to a lower layer of Child Tables.

21. The non-volatile memory device of claim 19, wherein the Entry Point'"'"'s address pointer data entry to the Root Table can be updated one or more times without overwriting the previous pointer data stored in the entry, each of the Root Table'"'"'s one or more address pointers data entries to the one or more Child Tables can be updated one or more times without overwriting the previous pointer data stored in the entry, and each of the one or more Child Table'"'"'s one or more address translation data entries can be updated one or more times without overwriting the previous translation data stored in the entry.

22. The non-volatile memory device of claim 19, wherein the hierarchal address translation data structure further comprises a Logical to Physical Erase Block Translation Table, where the one or more address translation entries in the one or more Child Tables contain a logical erase block ID, and where the control circuit is adapted to translate the logical erase block ID to a physical erase block utilizing the Logical to Physical Erase Block Translation Table.

23. The non-volatile memory device of claim 19, wherein the non-volatile memory array is further arranged into a plurality of erase blocks, each erase block containing a plurality of sectors.

24. The non-volatile memory device of claim 23, wherein the plurality of sectors are further arranged into clusters of sequential sectors.

25. The non-volatile memory device of claim 19, wherein the Entry Point is stored at known address location or stored within a defined Control Area of the non-volatile memory array.

26. The non-volatile memory device of claim 19, wherein the Entry Point stores one of configuration information or a pointer to configuration information for the non-volatile memory device.

27. The non-volatile memory device of claim 19, wherein the non-volatile memory is one of a NAND Flash memory device, a NOR Flash memory device, a Polymer memory device, a Ferroelectric Random Access Memory (FeRAM) device, an Ovionics Unified Memory (OUM) device, a Nitride Read Only Memory (NROM) device, a Carbon Nanotube Memory device, and a Magnetoresistive Random Access Memory (MRAM) device.

28. A non-volatile memory device, comprising:

a non-volatile memory array having a plurality of non-volatile memory cells and arranged into a plurality of erase blocks, each erase block containing a plurality of sectors; and

a control circuit, wherein the control circuit is adapted to access a logical address from the memory array by translating the logical address to a physical sector address of the memory array in reference to a hierarchal address translation data structure stored in the non-volatile memory array and to access a sector from the non-volatile memory array by translating a logical address of the sector to a physical sector address of the memory array in reference to a version number stored in a version number data field of the sector.

29. A Flash memory device, comprising:

a memory array having a plurality of non-volatile memory cells arranged in a plurality of erase blocks, each erase block containing a plurality of clusters of one or more consecutively addressed sectors; and

a control circuit, wherein the control circuit is adapted to access a logical address from the memory array by translating the logical address to a physical sector address of the memory array in reference to a hierarchal address translation data structure stored in the one or more erase blocks of the plurality of erase blocks; and

wherein the hierarchal address translation data structure comprises;

a Data_Root;

a Data_Map Table;

one or more consecutive sector group (CSG) Tables or one or more discrete sector group (DSG) Tables; and

wherein the Data_Root contains an address pointer data entry to the Data_Map Table, the Data_Map Table contains one or more address pointer data entries to the one or more CSG Tables or one or more DSG Tables, each of the one or more CSG Tables contain one or more address translation data entries to translate a logical address to a physical address of a cluster of consecutively address sectors, and each of the one or more DSG Tables contain one or more address translation data entries to translate a logical address to a physical address of a single sector cluster of a frequently updated sector.

30. The Flash device of claim 29, wherein the Data_Root'"'"'s address pointer data entry to the Data_Map Table can be updated one or more times without overwriting the previous pointer data stored in the entry, each of the Data_Map Table'"'"'s one or more address pointers data entries to the one or more CSG Tables or one or more DSG Tables can be updated one or more times without overwriting the previous pointer data stored in the entry, each of the one or more CSG Table'"'"'s one or more address translation data entries can be updated one or more times without overwriting the previous translation data stored in the entry, and each of the one or more DSG Table'"'"'s one or more address translation data entries can be updated one or more times without overwriting the previous translation data stored in the entry.

31. The Flash memory device of claim 30, wherein the control circuit is adapted to update the hierarchal address translation data structure when user data stored in the non-volatile memory array is updated by traversing up the hierarchal address translation data structure, updating the hierarchal address translation data structure further comprising:

checking if update space remains in an address translation data entry for the changed user data in a current CSG Table or DSG Table;

updating the address translation data entry when update space is available, and ending the update of the hierarchal address translation data structure;

creating a new CSG Table or DSG Table when the changed address translation data entry cannot be updated in the current CSG Table or DSG Table;

copying one or more most-current address translation entries to the new CSG Table or DSG Table;

checking if update space remains in an address pointer to the current CSG Table or DSG Table in the Data_Map Table;

updating the changed address pointer entry when update space is available, and ending the update of the hierarchal address translation data structure;

creating a new Data_Map Table when the changed address pointer entry cannot be updated in the Data_Map Table;

copying one or more most-current pointers to the new Data_Map Table;

checking if update space remains in an address pointer to the Data_Map Table in the Data_Root;

updating the changed address pointer entry when update space is available, and ending the update of the hierarchal address translation data structure;

creating a new Data_Root when the changed address pointer entry cannot be updated in the Data_Root; and

copying one or more most-current pointers to the new Data_Root.

32. The Flash memory device of claim 29, wherein the hierarchal address translation data structure further comprises a Block_ID erase block translation table, where the one or more address translation entries in the one or more CSG Tables or one or more DSG Tables contain a logical erase block ID, and where the control circuit is adapted to translate the logical erase block ID to a physical erase block utilizing the Block_ID Table.

33. The Flash memory device of claim 29, wherein the Flash memory device is one of a NAND Flash memory device and a NOR Flash memory device.

34. A Flash memory device, comprising:

a memory array having a plurality of non-volatile memory cells arranged in a plurality of erase blocks, each erase block containing a plurality of clusters of one or more consecutively addressed sectors; and

a control circuit, wherein the control circuit is adapted to access a logical address from the memory array by translating the logical address to a physical sector address of the memory array in reference to a hierarchal address translation data structure stored in the one or more erase blocks of the plurality of erase blocks; and

wherein the Flash memory device is adapted to access sectors in the memory array utilizing a version number address translation to retrieve the physical address in the memory array containing the most recent version of the accessed sector.

35. A system, comprising:

a host coupled to a non-volatile memory device, wherein the system is adapted to translate logical addresses to physical addresses in the non-volatile memory device utilizing hierarchal address translation data, where the hierarchal address translation data structure comprises;

an Entry Point;

a Root Table;

one or more Child Tables; and

wherein the Entry Point contains an address pointer data entry to the Root Table, the Root Table contains one or more address pointer data entries to the one or more Child Tables, and each of the one or more Child Tables contain one or more address translation data entries to translate a logical address to a physical address; and

wherein the system is adapted to update the hierarchal address translation data structure when user data stored in the non-volatile memory array is updated by traversing up the hierarchal address translation data structure, starting with the Child Table storing the changed address translation entry, updating the hierarchal address translation data structure further comprising;

checking if update space remains in a changed data entry or address pointer data entry in a current Table/data structure of a current level of the hierarchal address translation data structure;

updating the changed data entry or address pointer data entry when update space is available and ending the update of the hierarchal address translation data structure;

creating a new Table/data structure when the changed data entry cannot be updated in the current Table/data structure;

copying the most-current entries/pointers to the new Table/data structure,

ending the update of the hierarchal address translation data structure if the current Table/data structure is the Entry Point;

traversing up to a next level of the hierarchal address translation data structure if the current Table/data structure is not the Entry Point; and

repeating updating on a parent Table/data structure of the next level to change an address pointer in the parent Table/data structure from the current to the new Table/data structure.

36. The system of claim 35, wherein the non-volatile memory device comprises:

a memory array having a plurality of non-volatile memory cells arranged in a plurality of erase blocks, each erase block containing a plurality of sectors; and

a control circuit, wherein the control circuit is adapted to access a logical address from the memory array by translating the logical address to a physical sector address of the memory array in reference to a hierarchal address translation data structure stored in the one or more erase blocks of the plurality of erase blocks.

37. The system of claim 35, wherein the Entry Point'"'"'s address pointer data entry to the Root Table can be updated one or more times without overwriting the previous pointer data stored in the entry, each of the Root Table'"'"'s one or more address pointers data entries to the one or more Child Tables can be updated one or more times without overwriting the previous pointer data stored in the entry, and each of the one or more Child Table'"'"'s one or more address translation data entries can be updated one or more times without overwriting the previous translation data stored in the entry.

38. The system of claim 36, wherein the system is adapted to access logical sectors of data in the non-volatile memory device utilizing a cluster address translation to retrieve the physical address in the memory array of a cluster of consecutive sectors containing an accessed logical sector.

39. The system of claim 35, wherein the non-volatile memory is one of a NAND Flash memory device, a NOR Flash memory device, a Polymer memory device, a Ferroelectric Random Access Memory (FeRAM) device, an Ovionics Unified Memory (GUM) device, a Nitride Read Only Memory (NROM) device, and a Magnetoresistive Random Access Memory (MRAM) device.

40. A system, comprising:

a host coupled to a non-volatile memory device, wherein the system is adapted to translate logical addresses to physical addresses in the non-volatile memory device utilizing a hierarchal address translation data, where the hierarchal address translation data structure comprises;

an Entry Point;

a Root Table;

one or more Child Tables; and

wherein the Entry Point contains an address pointer data entry to the Root Table, the Root Table contains one or more address pointer data entries to the one or more Child Tables, and each of the one or more Child Tables contain one or more address translation data entries to translate a logical address to a physical address; and

wherein the hierarchal address translation data structure further comprises a Logical to Physical Erase Block Translation Table, where the one or more address translation entries in the one or more Child Tables contain a logical erase block ID, and where the system is adapted to translate the logical erase block ID to a physical erase block utilizing the Logical to Physical Erase Block Translation Table.

41. A system, comprising:

a host coupled to a non-volatile memory device, wherein the system is adapted to translate logical addresses to physical addresses in the non-volatile memory device utilizing hierarchal address translation data; and

wherein the non-volatile memory device comprises;

a memory array having a plurality of non-volatile memory cells arranged in a plurality of erase blocks, each erase block containing a plurality of sectors; and

a control circuit, wherein the control circuit is adapted to access a logical address from the memory array by translating the logical address to a physical sector address of the memory array in reference to a hierarchal address translation data structure stored in the one or more erase blocks of the plurality of erase blocks; and

wherein the system is adapted to access a sector from the non-volatile memory device by translating a logical address of the sector to a physical sector address of the memory array in reference to a version number stored in a version number data field of the sector.