Filter-based lock-in circuits for PLL and fast system startup

DC
  • US 7,515,003 B2
  • Filed: 05/30/2007
  • Issued: 04/07/2009
  • Est. Priority Date: 05/30/2007
  • Status: Expired due to Fees
First Claim
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1. A filter-based lock-in circuit used in a system for reducing system startup time and system latency time, comprising:

  • an upper transistor and a lower transistor connected in series between a power supply and ground having a shared terminal which becomes a single bidirectional node, wherein the shared terminal is defined by a junction between the upper transistor and the lower transistor;

    a sensing inverter for sensing a voltage at the single bidirectional node and comparing it with an input transition voltage of the sensing inverter which causes an output of the sensing inverter to be centered at half the power supply voltage wherein an input terminal of the sensing inverter is connected to the single bidirectional node;

    a logic gate coupled between an output terminal of the sensing inverter and a gate terminal of the upper transistor; and

    wherein an initial voltage at the single bidirectional node of the filter-based lock-in circuit is almost the same as the input transition voltage of the sensing inverter.

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