Memory control apparatus

• US 7,516,254 B2
• Filed: 09/07/2006
• Issued: 04/07/2009
• Est. Priority Date: 09/16/2005
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Sumida, Keizo, Nanki, Hidenori, Mino, Yoshiteru
• Primary Examiner(s): Patel; Niketa I
• Assistant Examiner(s): Borromeo; Juanito C
• Application Number:
  US11/470,742
• Publication Number:
  US 20070088855A1
• Time in Patent Office: 943 Days
• Field of Search: 710/22, 710/52
• US Class Current: 710/52
• CPC Class Codes: G06F 13/1631 through address comparison

Abstract

A memory control apparatus is capable of surely becoming consistent with an external memory while avoiding a deterioration in access efficiency to the external memory. The memory control apparatus includes: a data buffer and an address buffer which respectively store data and addresses related to past access requests from a first master; a first comparison unit which compares a new address with the address of the address buffer upon receiving the new address; a buffer control unit which performs one of issuing an access request to an external memory I/F or outputting the data in the data buffer to the first master, depending on the comparison result; a specific access detection unit which disables the contents of the data buffer irrespective of the comparison result.

Claims

1. A memory control apparatus which performs data transfer between a master and an external memory, said apparatus comprising:

a master interface operable to receive an access request from the master and issue the access request to the external memory; and

an external memory interface operable to receive the access request from said master interface and access the external memory,

wherein said master interface includes;

a data buffer operable to store data transferred from said external memory interface when the access request is issued;

an address buffer operable to store an address for which the access request has been issued;

a first comparison unit operable to compare a new address for which the access request has newly been issued with the address stored in said address buffer, and output first comparison information indicating whether or not the new address matches the address stored in said address buffer which indicates an address range of data stored in said data buffer;

a buffer control unit operable to issue an access request to said external memory interface, in the case where the first comparison information indicates a mismatch between the new address and the stored address, and operable to output data from said data buffer to the master without issuing an access request to said external memory interface, in the case where the first comparison information indicates a match between the new address and the stored address; and

a specific access detection unit operable to detect a new access request made by the master to a specific address on the external memory and determine, irrespective of whether the first comparison information indicates the match or the mismatch, whether or not to issue an access request to said external memory interface so as to control said buffer control unit based on the determination.

2. The memory control apparatus according to claim 1,

wherein said specific access detection unit includes:

a second comparison unit operable to compare the new address with the specific address on the external memory, and output, to said buffer control unit, second comparison information indicating whether or not the new address matches the specific address; and

a buffer disabling unit operable to disable a content of said address buffer and control said buffer control unit to make a dummy response to the access request, in the case where the second comparison information indicates a match between the new address and the specific address.

3. The memory control apparatus according to claim 2,

wherein the specific address is included in a specific area, on the external memory, where an access from the master is prohibited because the specific address is used by said external memory interface during access control.

4. The memory control apparatus according to claim 2,

wherein said specific access detection unit further includes

a specific address setting register where a specific address can be arbitrarily set.

5. The memory control apparatus according to claim 2, further comprising

a dummy access issuance unit operable to receive a notification indicating that shared data on the external memory has been updated, and issue, to said master interface, the access request the specific address.

6. The memory control apparatus according to claim 1,

wherein said specific access detection unit is operable to control said buffer control unit to forcibly issue or prohibit issuance of an access request to the external memory interface, depending on the comparison between the new address and an address in access history and irrespective of whether the first comparison information indicates the match or the mismatch.

7. The memory control apparatus according to claim 6,

wherein said specific access detection unit includes:

a buffer access history storage unit operable to store history information indicating whether the master accessed the external memory interface or the master accessed said data buffer;

a third comparison unit operable to compare the new address with the address stored in said address buffer, and output, to said buffer update unit, the third comparison information indicating whether or not the new address completely matches the stored address; and

a buffer update unit operable to control said buffer control unit to forcibly issue an access request to the external memory interface, in the case where the third comparison information indicates a match between the new address and the stored address and the history information of said buffer access history storage unit indicates an access to said data buffer.

8. The memory control apparatus according to claim 7, further comprising

a dummy access issuance unit operable to receive a notification indicating that shared data on the external memory has been updated, and issue, to said master interface an access request for an address stored in said address buffer.

9. The memory control apparatus according to one of claim 5 and claim 8,

wherein the master is a Direct Memory Access (DMA) controller,

the notification indicates an activation request for activating the DMA controller, and

said dummy access issuance unit is operable to control the DMA controller to start data transfer after the access request is issued at the time of receiving the notification.

10. The memory control apparatus according to claim 9,

wherein the DMA controller includes a plurality of channels,

the notification indicates an activation request for activating one of the plurality of channels,

said memory control apparatus further comprises

a dummy access control register where a value indicating “

enable”

or “

disable”

is set on a channel basis, and

said dummy access issuance unit is operable to prohibit issuance of the access request, in the case where the value set in said dummy access control register indicates “

disable”

with respect to the channel to which the activation request has been issued by the notification.

11. The memory control apparatus according to claim 9,

wherein the DMA controller includes a plurality of channels,

the notification indicates an activation request for activating one of the plurality of channels and an activation factor of the activation request,

said memory control apparatus further comprises

a dummy access control register where a value indicating “

enable”

or “

disable”

is set on an activation factor basis, said dummy access control register being shared among the channels, and

said dummy access issuance unit is operable to prohibit issuance of the access request, in the case where the value set in said dummy access control register indicates “

disable”

with respect to the activation factor indicated by the notification.

12. The memory control apparatus according to claim 6,

wherein said specific access detection unit includes:

an access history buffer operable to store access information including at least the address in the access history;

a fourth comparison unit operable to compare new access information, which includes at least the new address for which the new access request has been issued, with the access information stored in said access history buffer, and output the fourth comparison information indicating whether or not an identical access has been repeated; and

a buffer disabling unit operable to control said buffer control unit to forcibly issue an access request to said external memory interface, in the case where the fourth comparison information indicates that the identical access has been repeated.

13. The memory control apparatus according to claim 12,

wherein, when said buffer disabling unit controls said buffer control unit to issue an access request to said external memory interface,

said buffer disabling unit is operable to control said buffer control unit to issue an access request for requesting data corresponding to a request size indicated by the new access request, in the case where the fourth comparison information indicates that the access has been repeated, and

said buffer disabling unit is operable to control said buffer control unit to issue an access request for requesting data corresponding to a size of said data buffer, in the case where the fourth comparison information indicates that no identical access has been repeated.

14. The memory control apparatus according to claim 12, further comprising

a buffer update unit operable to update a content of said data buffer using data read out from said external memory interface, in the case where the fourth comparison information indicates that the identical access has been repeated.

15. The memory control apparatus according to claim 14,

wherein said external memory interface includes:

a polling address setting register where an address on the external memory can be arbitrarily set;

a polling access history storage unit operable to be set triggered by a read access and be reset triggered by a write access, the read access and the write access being made to the address which has been set in said polling address setting register; and

an external memory selection unit operable to prohibit an access to the external memory and make a response to said master interface within a time which is short compared to a time required in the case of accessing the external memory, in the case where said polling access history storage unit has been set by the time when said master interface makes a read access request for the address set in said polling address setting register, and

said specific access detection unit further includes

a buffer selection unit operable to control said buffer control unit to output data stored in said data buffer to the master, in the case where said external memory interface makes the response within a predetermined time period.

16. The memory control apparatus according to claim 15,

wherein said polling access history storage unit is operable to be reset triggered by a read access which said master interface makes to an address other than the polling address.

17. A memory control method for performing data transfer between a master and an external memory, using a memory control apparatus which includes:

a master interface which receives an access request from the master and issue the access request to the external memory; and

an external memory interface operable to receive the access request from the master interface and access the external memory,

wherein the master interface includes;

a data buffer which stores data transferred from the external memory interface when the access request is issued; and

an address buffer which stores an address for which the access request has been issued, and

wherein said memory control method comprises;

comparing a new address for which the access request has newly been issued with the address stored in the address buffer, and outputting first comparison information indicating whether or not the new address matches the address stored in said address buffer which indicates an address range of data stored in the data buffer;

issuing an access request to the external memory interface, in the case where the first comparison information indicates a mismatch between the new address and the stored address, and outputting data from the data buffer to the master without issuing an access request to the external memory interface, in the case where the first comparison information indicates a match between the new address and the stored address; and

detecting a new access request made by the master to a specific address on the external memory and determining, irrespective of whether the first comparison information indicates the match or the mismatch, whether or not to issue an access request to the external memory interface so as to control the buffer control unit based on the determination.