DRAM access transistor

• US 7,518,184 B2
• Filed: 06/26/2006
• Issued: 04/14/2009
• Est. Priority Date: 09/17/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Tran, Luan C.
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US11/474,362
• Publication Number:
  US 20060240634A1
• Time in Patent Office: 1,023 Days
• Field of Search: 257/330, 257/E29.26
• US Class Current: 257/330
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor
• CPC Class Codes: H10B 12/488 Word lines

Abstract

Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

Claims

1. A self-aligned recessed gate structure, comprising:

a gate layer which is conductive, comprising;

a first region having a first width, said first region being recessed below a surface of a semiconductor substrate; and

a second region having a second width, said second region extending above said surface of said semiconductor substrate;

a conductive layer located above and in conductive electrical connection with said second region of said gate layer;

a barrier layer separating said conductive layer from said second region of said gate layer, the barrier layer being conductive and through which said conductive layer is in conductive electrical connection with said second region of said gate layer;

an insulating layer located above said second region of said gate layer;

an oxide layer located on sidewalls and bottom of said gate layer; and

nitride spacers located along sidewalls of said second region of the gate layer but not along sidewalls of said first region of the gate layer, wherein said nitride spacers are in contact with said insulating layer, said barrier layer, and said oxide layer located on said sidewalls of said gate layer.

2. The self-aligned recessed gate structure of claim 1, wherein said gate layer comprises polysilicon material.

3. The self-aligned recessed gate structure of claim 1 wherein said conductive layer comprises a transition metal layer.

4. The self-aligned recessed gate structure of claim 1 wherein said insulating layer comprises a nitride cap material.

5. The self-aligned recessed gate structure of claim 1, wherein said conductive layer comprises a metal layer.

6. The self-aligned recessed gate structure of claim 1, wherein said conductive layer comprises a silicide.

7. A self-aligned recessed gate structure, comprising:

a first recessed gate region having a first width, said first recessed gate region being located below a surface of a semiconductor substrate;

a second gate region having a width of about 80 nm, said second gate region extending above said surface of said semiconductor substrate, wherein said second gate region comprises a gate layer, a conductive layer, and an insulating layer;

an oxide layer located on sidewalls and bottom of each of said gate layer and said first recessed gate region; and

insulating spacers located on sidewalls of said second gate region but not on said sidewalls of said first recessed gate region, wherein said insulating spacers are in contact with said insulating layer, said conductive layer and said oxide layer located on said sidewalls of said gate layer.

8. The self-aligned recessed gate structure of claim 7, wherein said first width is about 60 nm.

9. The self-aligned recessed gate structure of claim 7 wherein the conductive gate layer comprises a silicide.

10. The self-aligned recessed gate structure of claim 9, wherein said silicide is formed of a material selected from the group consisting of CoSi, TiSi, MoSi and NiSi.

11. The self-aligned recessed gate structure of claim 7, wherein said gate layer comprises a silicide and is formed of a material selected from the group consisting of CoSi, TiSi, MoSi and NiSi.

12. A memory cell, comprising:

a silicon substrate;

a transistor including a self-aligned recessed gate structure fabricated within said silicon substrate;

a doped region in said silicon substrate disposed adjacent to said gate structure; and

a capacitor formed over and electrically connected with said doped region,

wherein said self-aligned recessed gate structure further comprises;

a gate layer comprising;

a first region having a first width located below a surface of said silicon substrate; and

a second region having a second width greater than said first width, said second region extending above said surface of said silicon substrate;

a conductive layer located above said second region of said gate layer;

a barrier layer formed on the sidewalls and bottom of the conductive layer, the barrier layer separating said conductive layer from said second region of said gate layer;

an insulating layer located above said conductive region; and

an oxide layer located on the sidewalls and bottom said gate layer.

13. The memory cell of claim 12, wherein said second region extends above said surface of said silicon substrate by about 20 nm to about 800 nm.

14. The memory cell of claim 13, wherein said second region extends above said surface of said silicon substrate by about 200 nm.

15. The memory cell of claim 12, wherein said gate layer comprises a conductive material.

16. The memory cell of claim 15, wherein said conductive material is a silicide.

17. The memory cell of claim 16, wherein said silicide is formed of a material selected from the group consisting of CoSi, TiSi, MoSi and NiSi.

18. The memory cell of claim 16 wherein said insulating layer comprises a cap material over said silicide.

19. The memory cell of claim 18, wherein said cap material is formed of a nitride material or an etch-stop insulating material.

20. The memory cell of claim 12, wherein said memory cell is a DRAM memory cell.

21. The memory cell of claim 12, wherein said memory cell is part of a memory circuit coupled to a processor.

22. The memory cell of claim 21, wherein at least one of said processor and said memory circuit contains said gate structure.