Graphics processor with texture memory allocation system

• US 7,518,616 B1
• Filed: 07/15/1999
• Issued: 04/14/2009
• Est. Priority Date: 07/17/1998
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: 3DLabs Incorporated Limited (Creative Technology Ltd.)
• Inventors: Edwards, Stephen W.
• Primary Examiner(s): Brier, Jeffery A.
• Application Number:
  US09/353,887
• Time in Patent Office: 3,561 Days
• Field of Search: 345/430, 345/425, 345/429, 345/582, 345/552
• US Class Current: 345/582
• CPC Class Codes: G06T 1/60 Memory management

Abstract

A graphics accelerator for processing a graphical image includes a texture buffer for storing texture maps and data relating to the texture maps stored in the texture buffer, and a texture processor that performs texturing operations on the graphical image. The texture processor includes a fetching engine that retrieves texture packets, where each texture packet is stored in the texture buffer and associated with a texture map. Each texture packet includes data relating to the location of its associated texture map in the texture buffer.

Claims

1. A graphics accelerator for processing a graphical image, the graphics accelerator comprising:

a single texture buffer for storing texture maps and data relating to the texture maps stored in the texture buffer; and

a plurality of texture processors that perform texturing operations on the graphical image, the plurality of the texture processors retrieving texture packets from the single texture buffer,

each texture processor including a fetching engine that retrieves the texture packets, each texture packet being stored in the texture buffer and being associated with a texture map that is different than the texture maps associated with any other texture packet in the texture buffer, each texture packet including data relating to the location of its associated texture map in the texture buffer and data relating to the dimensional type of that texture packet'"'"'s associated texture map;

wherein at least one of said texture processors is configured to convert the associated texture map to a one dimensional texture map by defining a plurality of data blocks within the texture map and then assigning a sequence number to each of the data blocks; and

wherein if said data blocks are consecutive in the texture map, they are stored next to each other in memory locations.

2. The graphics accelerator as defined by claim 1 wherein the dimensional type of each texture map is one of a one dimensional texture map, a two dimensional texture map, and a three dimensional texture map.

3. The graphics accelerator as defined by claim 1 wherein the texture processor further includes:

an input for receiving a texture message indicating that a texture map is to be utilized by the texture processor, the fetching engine responsively retrieving selected texture packets from the single texture buffer in response to receipt of the texture message.

4. The graphics accelerator as defined by claim 3 wherein the texture processor further includes:

a parsing engine for parsing a fetched texture packet and determining information relating to the texture map associated with the fetched texture packet.

5. The graphics accelerator as defined by claim 4 wherein the information relates to the location in the texture buffer of the texture map associated with the fetched texture packet.

6. The graphics accelerator as defined by claim 4 wherein the information relates to the number of dimensions of the texture map associated with the fetched texture packet.

7. A method of storing a texture map in a single linear texture memory of a graphics accelerator, the method comprising:

A. determining the dimension of the texture map by a texture processor;

B. converting by the texture processor the texture map to a one dimensional texture map if the dimension of the texture map is determined to be more than one dimensional, the one dimensional texture map having a first number of data blocks which are consecutive to each other;

C. locating a second number of memory locations which are located next to each other in the single linear texture memory, the first number being equal to the second number; and

D. storing the one dimensional texture map in the located memory locations in the single linear texture memory;

wherein the texture map is two dimensional, step B comprising;

B1. defining a plurality of data blocks within the texture map; and

B2. assigning a sequence number to each of the data blocks, the sequence numbers being consecutive numbers; and

wherein step D comprises;

D1. consecutively storing each said data block of the one dimensional texture map in the located memory locations if said data blocks are consecutive to each other.

8. A graphics accelerator for processing graphical request code, the graphics accelerator comprising:

a single linear texture memory for storing texture maps;

a plurality of texture processors that applies textures to items to be displayed, the plurality of the texture processors retrieving texture packets from the single linear texture memory, each texture processor including a texture map converter that converts texture maps having dimensions greater than one dimensional to a one dimensional texture map, each dimensional texture map having a first number of data blocks which can be consecutive to each other, the texture processor further including means for locating a second number of memory locations which are located next to each other in the single linear texture memory, the first number being equal to the second number; and

means for storing the one dimensional texture map in the located memory locations in the single texture memory;

wherein the texture map converter comprises;

means for defining a plurality of data blocks within the texture map; and

means for assigning a sequence number to each of the data blocks, the sequence numbers being consecutive numbers; and

the storing means comprises;

means for consecutively storing each data block of the one dimensional texture map in the located memory locations if said data blocks are consecutive to each other.