Self-timed memory having common timing control circuit and method therefor

• US 7,518,947 B2
• Filed: 09/28/2006
• Issued: 04/14/2009
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Starnes, Glenn E.
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): RADKE, JAY W
• Application Number:
  US11/536,136
• Publication Number:
  US 20080080297A1
• Time in Patent Office: 929 Days
• Field of Search: 365/233, 365/233.1, 365/233.11, 365/194, 365/193, 365/233.5
• US Class Current: 365/233.11
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory comprises a memory array and a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an access to the memory array. A timing control circuit is coupled to the plurality of clock driver circuits. The timing control circuit includes a latch that is coupled to each of the plurality of clock driver circuits. The latch is for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal. The timing control circuit removes complex logic gates from the clock critical timing paths. Also, circuit topology is simplified allowing improved critical timing performance. Also, all of the clock driver circuits share a common latch control to improve clock recovery synchronization and reduce a risk of initializing the clock timing circuit in the wrong logic state.

Claims

1. A memory comprising:

a memory array having a plurality of memory cells;

an address decoder for selecting a memory cell in response to an address;

a data input/output circuit for transmitting data to or from the selected memory cell;

a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an operation of the address decoder and the data input/output circuit during an access to the memory array; and

a timing control circuit, coupled to the plurality of clock driver circuits, the timing control circuit having a first latch coupled to each of the plurality of clock driver circuits, the first latch for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a predetermined edge of a clock signal, the timing control circuit having a second latch coupled to the first latch, the second for restoring the first latch to an initial condition at the end of the memory access in response to a recovery signal.

2. The memory of claim 1, wherein the restoring of the first latch to the initial condition is independent of the clock signal.

3. The memory of claim 2, wherein the second latch comprises:

a first logic gate having a first input for receiving the recovery signal, a second input, and an output;

a second logic gate having a first input coupled to the output of the first logic gate, a second input for receiving the clock signal, and an output coupled to the second input of the first logic gate; and

a third logic gate having a first input for receiving an enable signal, a second input coupled to the output of the first logic gate, and an output coupled to an input of the first latch.

4. The memory of claim 3, wherein the first and second logic gates provide a NAND logic function and the third logic gate provides a NOR logic function.

5. The memory of claim 3, wherein the enable signal, when de-asserted, asynchronously resets the first latch to the initial condition.

6. The memory of claim 2, wherein each of the plurality of clock driver circuits comprises:

a logic gate having a first input coupled to receive the clock signal, a second input coupled to receive a clock enable signal, and a third input coupled to the first latch, and an output; and

a buffer circuit having an input coupled to the output of the logic gate, and an output for providing a corresponding one of the clock driver signals.

7. The memory of claim 6, wherein the logic gate provides a one stage AND-OR-INVERT logic function.

8. The memory of claim 2, wherein the memory array is organized as a plurality of blocks of memory cells, wherein each block of the plurality of blocks of memory cells comprises a local recovery circuit, and wherein the local recovery circuit of an active block of the plurality of blocks of memory cells asserts the recovery signal at completion of a memory access.

9. The memory of claim 8, wherein each of the local recovery circuits comprises:

a delay element for tracking a propagation delay of an access operation to a selected block of the plurality of blocks of memory cells; and

a tristateable buffer circuit, coupled to the delay element, for providing the recovery signal.

10. A memory comprising:

a memory array having a plurality of memory cells;

a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an access operation to the memory array;

a timing control circuit, coupled to the plurality of clock driver circuits, the timing control circuit having a first latch coupled to each of the plurality of clock driver circuits, the first latch for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal; and

a recovery circuit comprising a second latch, the second latch coupled to the first latch, the second latch receiving a recovery signal, the recovery signal being asserted in response to completion of the access operation to the memory array, wherein the second latch is for restoring the first latch to an initial condition in response to the recovery signal, and wherein the restoring of the first latch to the initial condition is independent of the clock signal.

11. The memory of claim 10, wherein the second latch comprises:

a first NAND logic gate having a first input for receiving the recovery signal, a second input, and an output;

a second NAND logic gate having a first input coupled to the output of the first logic gate, a second input for receiving the clock signal, and an output coupled to the second input of the first logic gate; and

a NOR logic gate having a first input for receiving an enable signal, a second input coupled to the output of the first NAND logic gate, and an output coupled to an input of the first latch.

12. The memory of claim 11, wherein the enable signal, when de-asserted, asynchronously resets the first latch to the initial condition.

13. The memory of claim 10, wherein each of the plurality of clock driver circuits comprises:

a one stage AND-OR-INVERT logic gate having a first input coupled to receive the clock signal, a second input coupled to receive a clock enable signal, and a third input coupled to the first latch, and an output; and

a buffer circuit having an input coupled to the output of the one stage AND-OR-INVERT logic gate, and an output for providing a corresponding one of the clock driver signals.

14. The memory of claim 10, wherein the memory array is organized as a plurality of blocks of memory cells, wherein each block of the plurality of blocks of memory cells comprises a local recovery circuit, and wherein the local recovery circuit of an active block of the plurality of blocks of memory cells asserts the recovery signal at completion of a memory access.

15. The memory of claim 14, wherein each of the local recovery circuits comprises:

a delay element for tracking a propagation delay of an access operation to a selected block of the plurality of blocks of memory cells; and

a tristateable buffer circuit, coupled to the delay element, for providing the recovery signal.

16. The memory of claim 10, wherein the memory is characterized as being a self-timed memory.

17. A method comprising:

providing a memory having a memory array with a plurality of memory cells;

coupling a clock signal to the memory;

providing a plurality of clock driver circuits for timing an access to the memory array in response to a predetermined edge of the clock signal;

providing a latch for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to the first predetermined edge of the clock signals;

generating a recovery siginal at completion of the access to the memory array;

and

restoring the latch to an initial condition in response to the recovery signal, and

wherein the restoring of the latch to the initial condition is independent of the clock signal.

18. The method of claim 17, wherein generating a recovery signal further comprises tracking a propagation delay of the access to the memory array to determine when the access to the memory array is complete.

19. The method of claim 17, further comprising asynchronously ending the access to the memory array before completion of the access.