Radiation-hardened silicon-on-insulator CMOS device, and method of making the same

• US 7,524,710 B2
• Filed: 06/06/2008
• Issued: 04/28/2009
• Est. Priority Date: 04/05/2001
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Lyons, Eugene F., Miscione, Anthony M., Imthurn, George, Stuber, Michael A.
• Primary Examiner(s): Purvis; Sue A
• Assistant Examiner(s): Erdem; Fazli
• Application Number:
  US12/134,681
• Publication Number:
  US 20080230837A1
• Time in Patent Office: 326 Days
• Field of Search: 438/149, 438/151, 438/254, 438/164, 438/166, 257/347, 257/352, 257/E21.41, 257/E21.61, 257/E21.704, 257/E27.111
• US Class Current: 438/154
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.

Claims

1. A method of radiation hardening an ultrathin silicon on sapphire P-channel transistor including the act of:

implanting an N-type impurity into a P-channel of the transistor with sufficient implant energy and at a sufficient dosage to produce a peak doping concentration within the sapphire substrate that is at least 10 times greater than a peak N-type impurity concentration within the silicon layer and that is disposed at least 0.05 microns from a silicon-sapphire back channel interface.

2. The method of claim 1,

wherein the implant energy and dosage are sufficient to produce a peak doping concentration within the sapphire substrate that is at least 10 times greater than a peak N-type impurity concentration within the silicon layer and that is disposed at least 0.10 microns from a silicon-sapphire back channel interface.

3. The method of claim 1,

wherein the implant energy is at least 400 keV.

4. The method of claim 1,

wherein the N-type impurity implant dosage is approximately 1.0×

1014 ions/cm2.

5. The method of claim 1,

wherein the implant energy is approximately 400 keV;

and

wherein the N-type impurity implant dosage is approximately 1.0×

1014 ions/cm2.

6. The method of claim 1 further including:

performing a subsequent implantation of an N-type impurity to set a desired voltage threshold.

7. The method of claim 1 further including:

performing a subsequent implantation of an N-type impurity to set a desired voltage threshold;

wherein a first N-type impurity is used for the implantation of a peak concentration within the sapphire and a second N-type impurity is used for the subsequent implantation to set a desired voltage threshold.

8. A radiation hardened ultrathin silicon on sapphire P-channel transistor product produced by a process comprising the steps of:

implanting an N-type impurity into a P-channel of the transistor with sufficient implant energy and at a sufficient dosage to produce a peak doping concentration within the sapphire substrate that is at least 10 times greater than a peak N-type impurity concentration within the silicon layer and that is disposed at least 0.05 microns from a silicon-sapphire back channel interface.

9. The product of claim 8,

wherein the implant energy and dosage are sufficient to produce a peak doping concentration within the sapphire substrate that is at least 10 times greater than a peak N-type impurity concentration within the silicon layer and that is disposed at least 0.10 microns from a silicon-sapphire back channel interface.

10. The product of claim 8,

wherein the implant energy is at least 400 keV.

11. The product of claim 8,

wherein the N-type impurity implant dosage is approximately 1.0×

1014 ions/cm2.

12. The product of claim 8,

wherein the implant energy is approximately 400 keV;

and

wherein the N-type impurity implant dosage is approximately 1.0×

1014 ions/cm2.

13. The product of claim 8 further including:

performing a subsequent implantation of an N-type impurity to set a desired voltage threshold.

14. The product of claim 8 further including:

performing a subsequent implantation of an N-type impurity to set a desired voltage threshold;

wherein a first N-type impurity is used for the implantation of a peak concentration within the sapphire and a second N-type impurity is used for the subsequent implantation to set a desired voltage threshold.