Method for fabricating high performance leadframe in electronic package

• US 7,528,013 B1
• Filed: 12/16/2004
• Issued: 05/05/2009
• Est. Priority Date: 11/12/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Santo, Hendrick, Kao, Vincent, Sutardja, Sehat
• Primary Examiner(s): Nguyen; Khiem D
• Application Number:
  US11/016,443
• Time in Patent Office: 1,601 Days
• Field of Search: 438/106, 438/111, 438/123, 438/124, 438/127, 438/FOR.366, 257/666, 257/784, 257/786, 257/773, 257/787, 257/E21.506, 257/E21.511, 257/E23.031, 257/E23.042, 257/E23.057, 257/E23.066
• US Class Current: 438/123
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48253 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49179 Corner adaptations, i.e. disposition of the wire connectors at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

Systems and techniques to provide a high performance leadframe architecture in electronic packages. An electronic package includes an extended area for wire bonding to provide improved high-current operation. The extended area can be an extended portion of a single lead in a single-layer non-leaded leadframe, where multiple wires are connected between multiple bond pads and the single lead. The extended area can be a support bar of a leadframe that is used as bond area for ground connections in a single-layer non-leaded leadframe. The extended area can be lead regions used for wire bonding voltage output and voltage input using a reduced power dissipation topology.

Claims

1. A method comprising:

forming a leadframe comprising a single layer of an electrically conducting material, a plane die paddle, support bars on first opposite sides of an electronic package, and a plurality of leads electrically isolated from each other;

applying metal plating to at least one of the support bars;

mounting a semiconductor chip including signal bond pads and ground bond pads on the plane die paddle;

connecting first wires between the signal bond pads and the plurality of leads;

connecting second wires between the ground bond pads and the at least one of the support bars that serves as a common ground; and

creating the electronic package that leaves the plurality of leads partially exposed at a bottom side of the electronic package providing surface mounting connections.

2. The method of claim 1, wherein said creating further comprises leaving the support bars and the plane die paddle partially exposed on the bottom of the electronic package to serve as the common ground.

3. The method of claim 2, wherein said creating further comprises leaving the support bars partially exposed at edges of the electronic package on the first opposite sides.

4. The method of claim 3, wherein the partially exposed edges of the support bars comprise two or more exposed portions on at least one of the first opposite sides of the electronic package.

5. A method comprising:

forming a leadframe comprising a plane die paddle, control leads electrically isolated from each other, voltage output leads electrically connected together, and voltage input leads electrically connected together, wherein the connected voltage output leads are positioned closer to the plane die paddle than the connected voltage input leads; and

mounting a semiconductor chip including control bond pads, voltage output bond pads, and voltage input bond pads, on the plane die paddle;

connecting control wires between the control bond pads and the control leads;

connecting voltage output wires between the voltage output bond pads and the connected voltage output leads; and

connecting voltage input wires between the voltage input bond pads and the connected voltage input leads, wherein the voltage output wires are shorter than the voltage input wires.

6. The method of claim 5, wherein the semiconductor chip includes ground bond pads, the method further comprising connecting ground wires between the ground bond pads and a common ground region, wherein the common ground region includes the plane die paddle, and the ground wires are shorter than the voltage output wires.

7. The method of claim 6, wherein the connected voltage output leads comprise a first region, the connected voltage input leads comprise a second region, the second region being smaller than the first region, and the first region being smaller than the common ground region.

8. The method of claim 7, wherein the connected voltage output leads straddle the connected voltage input leads.