Single level cell programming in a multiple level cell non-volatile memory device

• US 7,529,129 B2
• Filed: 02/22/2008
• Issued: 05/05/2009
• Est. Priority Date: 12/09/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US12/035,552
• Publication Number:
  US 20080144373A1
• Time in Patent Office: 438 Days
• Field of Search: 365/185.03, 365/185.11, 365/185.12, 365/168
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation the programs reinforcing data that adjusts the threshold level of the cell to the appropriate level for the desired data.

Claims

1. A method for single level programming in a multiple level memory cell, the method comprising:

writing single level data to one of a plurality of bits of the memory cell; and

writing reinforcing data to the remaining plurality of bits of the memory cell such that a threshold voltage of the memory cell is adjusted to one of two desired threshold voltages representing the single level data.

2. The method of claim 1 wherein the one of the plurality of bits is a least significant bit of the memory cell.

3. The method of claim 1 wherein the one of the plurality of bits is a most significant bit of the memory cell.

4. The method of claim 1 wherein the one of the plurality of bits is not a least or a most significant bit of the memory cell.

5. The method of claim 1 wherein the single level data is accompanied by an indicator bit identifying data as single level or multilevel data.

6. The method of claim 5 further comprising storing data as single level data or multilevel data in the multilevel memory cell in response to the indicator bit.

7. A method for programming single level data in a multilevel memory cell, comprising:

assigning a first memory cell level to represent single level data having a first level;

assigning a second memory cell level to represent single level data having a second level wherein a third memory cell level exists between the first memory cell level and the second memory cell level; and

programming the memory cell to one of the first or second memory cell levels representative of the level of the single level data.

8. The method of claim 7 wherein the first memory cell level represents an erased state of the memory cell.

9. The method of claim 7 further comprising assigning the first memory cell level to represent a most negative threshold level of the memory cell.

10. The method of claim 7 further comprising assigning the second memory cell level to represent a most positive threshold level of the memory cell.

11. The method of claim 7 further comprising programming data to the memory cell as single level data in response to an indicator bit identifying the data as single level data.

12. The method of claim 11 further comprising programming data in the memory cell as multilevel data in response to the indicator bit identifying the data as multilevel data.

13. The method of claim 7 further comprising reading the memory cell and mapping the read data to the first level of single level data if the memory cell is programmed to the first memory cell level and mapping the read data to the second level of single level data if the memory cell is programmed to the second memory cell level.

14. A method for programming a single bit of data in a multilevel memory cell having more than two data states wherein each data state is represented by a range of threshold voltages of the memory cell, comprising:

programming the multilevel cell to only one of two data states of the more than two data states such that a first data state of the more than two data states represents a most negative threshold voltage of the memory cell and a second data state of the more than two data states represents a most positive threshold voltage of the memory cell.

15. The method of claim 14 wherein one or more data states exist between the first and second data states.

16. A method for programming an array of multilevel cells with multilevel and single level data wherein the data is represented by a plurality of bits each bit representing a level, comprising:

programming single level data to a multilevel cell by programming one bit of the multilevel cell to one of two threshold levels such that the two threshold levels comprise the least and greatest threshold levels of the memory cell;

programming multilevel data to a memory cell by programming the cell to one of a plurality of levels wherein each level is representative of the multilevel data; and

programming a least significant bit of the multilevel data to a memory cell and a most significant bit of the multilevel data to a different memory cell.

17. A memory device, comprising:

an array of multilevel memory cells each memory cell configured to store multilevel data comprising a plurality of bits of data wherein each bit has a logical address; and

control circuitry configured to program each logical address to a different memory cell of the array of memory cells such that no adjacent logical addresses are stored in the same memory cell; and

wherein the control circuitry is further configured to determine if data to be stored is one of single level data and multilevel data and to program single level data to a memory cell to one of two levels such that the two levels comprise a least and a greatest threshold potential of the memory cell wherein at least a third level is present between the two levels and program multilevel data to a memory cell to a threshold potential representative of the multilevel data.

18. The memory device of claim 17 wherein the data to be stored comprises an indicator having a state which indicates that the data is one of either single level data or multilevel data.

19. The memory device of claim 18 wherein the control circuitry determines if the data is one of either single level data or multilevel data in response to the state of the indicator.

20. The memory device of claim 18 wherein the indicator comprises an indicator bit.