Driver voltage adjuster

• US 7,532,194 B2
• Filed: 02/03/2004
• Issued: 05/12/2009
• Est. Priority Date: 02/03/2004
• Status: Expired due to Fees

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: IDC, LLC
• Inventors: Chui, Clarence
• Primary Examiner(s): LEWIS, DAVID LEE
• Application Number:
  US10/772,120
• Publication Number:
  US 20050168431A1
• Time in Patent Office: 1,925 Days
• Field of Search: 345 55-109, 345204-214
• US Class Current: 345/108
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 3/3466 based on interferometric effect

Abstract

A display system uses a standardized display driver to provide row and column address voltages. The row and address column voltages are used by an array of interferometric elements through a voltage adjuster to adjust the row address voltages to provide adjusted row address voltages to the array of interferometric elements.

Claims

1. A display system, comprising:

a standardized display driver to provide address voltages;

an array of interferometric elements; and

a voltage adjuster to adjust address voltages to provide adjusted row address voltages to the array of interferometric elements,

wherein the voltage adjuster further comprises a resistor divider network configured to lower the address voltage amplitudes that are provided by the standardized display driver.

2. The display system of claim 1, the standardized display driver further comprising a driver for a liquid crystal display.

3. The display system of claim 1, the may of interferometric elements further comprising an array of iMoD™

elements.

4. The display system of claim 1, the voltage adjuster to adjust row address voltages.

5. The display system of claim 1, the voltage adjuster to adjust column address voltages.

6. A method of manufacturing an array of modulator elements and an adjuster circuit, comprising:

depositing a first metal layer on a transparent substrate;

patterning and etching the first metal layer to form electrodes;

depositing an optical stack layer;

depositing a first sacrificial layer upon the optical stack layer;

depositing a second metal layer on the sacrificial layer;

patterning and forming the second metal layer to form modulator elements;

forming a resistor divider network configured to lower address voltage amplitude that are provided from a standardized display driver; and

forming resistors from one metal layer and connecting the resistors with a subsequent metal layer.

7. The method of claim 6, forming the resistors from one metal layer further comprising forming the resistors from the first metal layer and connecting the resistors with the second metal layer.

8. The method of claim 6, further comprising:

depositing a second sacrificial layer;

depositing a third metal layer on the second sacrificial layer; and

patterning and etching the third metal layer to form posts and supports.

9. The method of manufacturing of claim 6, wherein the resistor divider network is formed on the first metal layer.

10. The method of claim 6 forming the resistors further comprising forming the resistors from the second metal layer and connecting the resistors using the third metal layer.

11. The method of claim 6, further comprising:

depositing a third sacrificial layer;

depositing a fourth metal layer on the third sacrificial layer;

patterning and etching the fourth metal layer to form a bus layer.

12. The method of claim 6, forming the resistors from one metal layer further comprising forming the resistors from the first metal layer and connecting the resistors using the fourth metal layer.

13. The method of claim 6, forming the resistors from one metal layer further comprising forming the resistors from the second metal layer and connecting the resistors using the fourth metal layer.

14. The method of claim 6, forming the resistors from one metal layer further comprising forming the resistors from the third metal layer and connecting the resistors using the fourth metal layer.

18. The method of manufacturing of claim 6, wherein the resistor divider network is formed on the same substrate of the array.

19. The method of claim 6, forming the resistors further comprising forming the resistors from the first metal layer and connecting the resistors using the third metal layer.

20. The method of manufacturing of claim 6, wherein the resistor divider network is formed on the second metal layer.

15. A resistor network, comprising:

an incoming address line;

a first resistor connected between the address line and a conductive bus; and

a second resistor connected between the address line and an adjusted address line,

wherein the resistor network lowers address voltage amplitudes provided by a

standardized display driver.

16. The resistor network of claim 15 the address line further comprising a row address line.

17. The resistor network of claim 15, the address line further comprising a column address line.