Semiconductor memory device and control method of the same
First Claim
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1. A semiconductor memory device comprising:
- a memory cell array;
a voltage generating circuit;
a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter; and
a control circuit which controls, when a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase at least an erase verify level in accordance with the parameter.
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Abstract
A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase at least an erase verify level in accordance with the parameter.
28 Citations
17 Claims
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1. A semiconductor memory device comprising:
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a memory cell array; a voltage generating circuit; a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter; and a control circuit which controls, when a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase at least an erase verify level in accordance with the parameter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A control method of a semiconductor memory device including a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter, and a control circuit which controls the voltage generating circuit, the method comprising:
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causing the control circuit to check whether a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, thereby detecting deterioration information of the memory cell array; changing, if the pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the parameter in a manner to increase at least an erase verify level; and controlling the voltage generating circuit in a manner to apply the erase voltage to the memory cell array by using the changed parameter, and executing an erase operation. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification