Tri-state output driver arranging method and memory device using the same

• US 7,532,538 B2
• Filed: 12/06/2006
• Issued: 05/12/2009
• Est. Priority Date: 01/13/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Seouk-Kyu, Jeong, Woo-Pyo
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): Hidalgo; Fernando N
• Application Number:
  US11/567,664
• Publication Number:
  US 20070165475A1
• Time in Patent Office: 888 Days
• Field of Search: 365/233.13, 365/230.06, 365/189.03, 365/189.15, 365/189.18, 365/189.05
• US Class Current: 365/230.06
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

A memory device includes a first sensing amplifier to amplify data received from the memory array, a first driver to generate a first tri-state signal responsive to the amplified data from an first sense amplifier and to provide the first tri-state signal to a data bus line, a second sensing amplifier to amplify data received from the memory array, and a second driver to generate a second tri-state signal responsive to the amplified data from an second sense amplifier and to provide the second tri-state signal to the data bus line, where the first sensing amplifier and the first driver are located in different regions of the device, and the second sensing amplifier and the second driver are located in a common region of the device.

Claims

1. A device comprising:

a first sensing amplifier to amplify data received from a memory array;

a first driver to generate a first tri-state signal responsive to the amplified data from the first sensing amplifier and to provide the first tri-state signal to a data bus line;

a second sensing amplifier to amplify data received from the memory array; and

a second driver to generate a second tri-state signal responsive to the amplified data from the second sensing amplifier, and to provide the second tri-state signal to the data bus line, where a first output loading on the first sensing amplifier as affected by the first driver is different from a second output loading on the second sensing amplifier as affected by the second driver, and where the first driver and the second driver provide a substantially equal load to the data bus line.

2. The device of claim 1 where the data bus line receives the first tri-state signal from the first driver and the second tri-state signal from the second driver at a substantially common location on the data bus line.

3. The device of claim 1 where the first driver includes

a first transistor configured to output a supply voltage to the data bus line responsive to a first output signal from the first sensing amplifier;

a second transistor configured to output a ground voltage to the data bus line responsive to a second output signal from the first sensing amplifier,

wherein the first transistor and second transistor are configured to provide a floating tri-state output responsive to the first output signal and the second output signal.

4. The device of claim 3 wherein the first sensing amplifier includes

a NAND gate to generate the first output signal responsive to a control signal and a first data signal from the memory array;

a first inverter to invert the first data signal from the memory array;

a second NAND gate to generate an internal signal by performing a NAND operation on the control signal and a inverted first data signal; and

a second inverter to generate the second output signal by inverting the internal signal.

5. The device of claim 4, wherein:

a first input terminal of the NAND gate is structured to receive the control signal;

a second input terminal of the NAND gate is structured to receive the first data signal;

an input terminal of the first inverter is directly coupled to the second input terminal of the NAND gate to receive the first data signal;

an output terminal of the first inverter is directly coupled to a first input terminal of the second NAND gate; and

a second input terminal of the second NAND gate is directly coupled to the first input terminal of the NAND gate to receive the control signal.

6. The device of claim 5, wherein:

an output terminal of the NAND gate is coupled to a gate of the first transistor;

an output terminal of the second NAND gate is directly coupled to an input terminal of the second inverter; and

an output terminal of the second inverter is coupled to a gate of the second transistor.

7. The device of claim 1 where the second driver includes

a first transistor configured to output a supply voltage to the data bus line responsive to a first output signal from the second sensing amplifier;

a second transistor configured to output a ground voltage to the data bus line responsive to a second output signal from the second sensing amplifier,

wherein the first transistor and second transistor are configured to provide a floating tri-state output responsive to the first output signal and the second output signal.

8. The device of claim 7 where the second sensing amplifier includes

a NAND gate to generate the first output signal responsive to a control signal and a first data signal from the memory array;

a first inverter to invert the first data signal from the memory array;

a second NAND gate to generate an internal signal by performing a NAND operation on the control signal and a inverted first data signal; and

a second inverter to generate the second output signal by inverting the internal signal.

9. The device of claim 8, wherein:

a first input terminal of the NAND gate is structured to receive the control signal;

a second input terminal of the NAND gate is structured to receive the first data signal;

an input terminal of the first inverter is directly coupled to the second input terminal of the NAND gate to receive the first data signal;

an output terminal of the first inverter is directly coupled to a first input terminal of the second NAND gate; and

a second input terminal of the second NAND gate is directly coupled to the first input terminal of the NAND gate to receive the control signal.

10. The device of claim 9, wherein:

an output terminal of the NAND gate is coupled to a gate of the first transistor;

an output terminal of the second NAND gate is directly coupled to an input terminal of the second inverter; and

an output terminal of the second inverter is coupled to a gate of the second transistor.

11. A method comprising:

arranging a first sensing amplifier and a first driver responsive to amplified data

from the first sensing amplifier, the first driver generating a first tri-state output signal on a data bus line; and

arranging a second sensing amplifier and a second driver responsive to amplified data from the second amplifier, the second driver generating a second tri-state output signal on the data bus line,

where a first output loading on the first sensing amplifier as affected by the first driver is different from a second output loading on the second sensing amplifier as affected by the second driver, and

where the second tri-state output loads the data bus line substantially the same as the first tri-state output.

12. The method of claim 11 where the data bus line receives the first tri-state signal from the first driver and the second tri-state signal from the second driver at a substantially common location on the data bus line.