Method and apparatus for providing secure programmable logic devices

  • US 7,536,559 B1
  • Filed: 05/05/2005
  • Issued: 05/19/2009
  • Est. Priority Date: 05/05/2005
  • Status: Active Grant
First Claim
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1. Apparatus for securing an integrated circuit device having instruction register logic coupled to control logic via an instruction bus, comprising:

  • a non-volatile memory for storing at least one security bit for at least one instruction associated with said programmable logic device; and

    gating logic in communication with said non-volatile memory and at least a portion of said instruction bus, said gating logic configured to selectively gate decoded instructions transmitted from said instruction register logic towards said control logic based on state of said at least one security bit.

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