Methods of forming semiconductor devices, assemblies and constructions

• US 7,537,994 B2
• Filed: 08/28/2006
• Issued: 05/26/2009
• Est. Priority Date: 08/28/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yang, Xiawan, Taylor, Ted
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Mitchell; James M
• Application Number:
  US11/511,596
• Publication Number:
  US 20080048298A1
• Time in Patent Office: 1,002 Days
• Field of Search: None
• US Class Current: 438/259
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material

Abstract

Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Claims

1. A method of forming a transistor, comprising:

providing a semiconductor material;

defining a line across the semiconductor material, the line having a narrow region between wide regions, the line having a pair of opposing sides;

forming a pair of trenches along opposing sides of the line;

forming protective material along sidewalls of the trenches to narrow the trenches;

isotropically etching the semiconductor material through the trenches to merge the trenches under the narrow region without merge the trenches under the wide regions;

forming gate dielectric along the narrow region of the line;

forming electrically conductive gate material within the trenches and under the narrow region;

conductively-doping the wide regions of the line of the semiconductor material to form a pair of source/drain regions;

such pair of source/drain regions being spaced from one another by a channel region comprised by the narrow region of the line of the semiconductor material;

wherein the narrow portion of the line has an outer periphery; and

wherein the gate material is a transistor gate entirely surrounding the outer periphery of the narrow portion of the line.

2. The method of claim 1 wherein the protective material is removed prior to forming the gate dielectric;

and wherein the gate dielectric is formed to entirely surround the narrow region of the line.

3. The method of claim 1 wherein the semiconductor material is monocrystalline silicon, and wherein the gate material comprises at least one composition selected from the group consisting of metal, metal compounds, and conductively-doped semiconductor material.

4. The method of claim 1 wherein the gate material comprises conductively-doped semiconductor material formed by:

depositing semiconductor material within the merged trenches; and

in situ doping the semiconductor material as it is deposited within the merged trenches.

5. The method of claim 1 wherein the gate material comprises conductively-doped semiconductor material formed by:

depositing semiconductor material within the merged trenches; and

implanting conductive-enhancing dopant into deposited semiconductor material.