Semi-static flip-flops for RFID tags

• US 7,541,843 B1
• Filed: 07/20/2006
• Issued: 06/02/2009
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Hara, Dennis Kiyoshi, Dressler, David D., Hyde, John D.
• Primary Examiner(s): Chang; Daniel D
• Application Number:
  US11/490,671
• Time in Patent Office: 1,048 Days
• Field of Search: 326/105, 340/572.4, 340/572.1, 340/5.65, 235/492
• US Class Current: 326/105
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/2948 Iterative decoding H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/6561 Parallelized implementations

Abstract

A radio frequency identification (RFID) circuit including a semi-static flip-flop having a static storage time longer than its dynamic storage time. The RFID circuit may include a timing block circuit to provide a timing block clock signal to the semi-static flip-flop, the signal having a first clock state duration shorter than the dynamic storage time and a second clock state duration longer than the dynamic storage time.

Claims

1. A radio frequency identification (RFID) circuit, including:

a first semi-static flip-flop having a first dynamic storage time and a first static storage time longer than the first dynamic storage time; and

a first timing block circuit operable to provide a first timing block clock signal to the first semi-static flip-flop, the first timing block clock signal having a first clock state duration shorter than the first dynamic storage time and a second clock state duration longer than the first dynamic storage time.

2. The circuit of claim 1, further including:

an oscillator operable to provide a high-frequency clock having a frequency higher than a frequency of the timing block clock signal, in which the timing block clock signal is derived from the high-frequency clock.

3. The circuit of claim 1, further including:

an antenna terminal operable to receive forward link data; and

a first operational sub-block operable to process the forward link data, wherein the first semi-static flip-flop is operable to control the flow of the forward link data through the first operational sub-block.

4. The circuit of claim 3, wherein the first operational sub-block comprises at least one of a symbol encoder and a symbol decoder.

5. The circuit of claim 3, wherein the first operational sub-block comprises a state machine.

6. The circuit of claim 3, wherein the first operational sub-block comprises a memory interface.

7. The circuit of claim 3, wherein the timing block clock signal is derived from forward link data.

8. The circuit of claim 7, wherein the timing block clock signal is derived from an express timing instruction included in the forward link data.

9. The circuit of claim 7, wherein the timing block clock signal is derived from symbols included in the forward link data.

10. The circuit of claim 3, further including:

a second semi-static flip-flop;

a second timing block circuit operable to provide a second timing block clock signal to the second semi-static flip-flop; and

a second operational sub-block to process a portion of the forward link data, wherein the second semi-static flip-flop controls the flow of the portion of the forward link data through the second operational sub-block.

11. The circuit of claim 10, wherein a first clock state duration of the second timing block clock signal is substantially the same as the first clock state duration of the timing block clock signal, and wherein a phase of the second timing block clock signal is not the same as a phase of the first timing block clock signal.

12. The circuit of claim 10, wherein a phase of the second timing block clock signal is substantially the same as a phase of the first timing block clock signal, and wherein a first clock state duration of the second timing block clock signal is not the same as the first clock state duration of the first timing block clock signal.

13. The circuit of claim 10, wherein a first clock state duration of the second timing block clock signal is not the same as the first clock state duration of the first timing block clock signal, and wherein a phase of the second timing block clock signal is not the same as a phase of the first timing block clock signal.

14. A radio frequency identification (RFID) tag, including:

an antenna operable to receive a wireless signal having encoded symbols;

a symbol detector operable to detect the encoded symbols of the wireless signal;

a first semi-static flip-flop to couple to the symbol detector and having a first dynamic storage time and a first static storage time longer than the first dynamic storage time; and

a first timing block circuit operable to provide a first timing block clock signal to the first semi-static flip-flop, the first timing block clock signal having a first clock state duration shorter than the first dynamic storage time and a second clock state duration longer than the first dynamic storage time.

15. The RFID tag of claim 14, further including:

an oscillator operable to provide a high-frequency clock having a frequency higher than a frequency of the timing block clock signal, in which the timing block clock signal is derived from the high-frequency clock.

16. The RFID tag of claim 14, further including:

an antenna terminal operable to receive forward link data; and

a first operational sub-block operable to process the forward link data, wherein the first semi-static flip-flop is operable to control the flow of the forward link data through the first operational sub-block.

17. The RFID tag of claim 16, wherein the first operational sub-block comprises at least one of a symbol encoder and a symbol decoder.

18. The RFID tag of claim 16, wherein the first operational sub-block comprises a state machine.

19. The RFID tag of claim 16, wherein the first operational sub-block comprises a memory interface.

20. The RFID tag of claim 16, further including:

a second semi-static flip-flop;

a second timing block circuit operable to provide a second timing block clock signal to the second semi-static flip-flop; and

a second operational sub-block to process a portion of the forward link data, wherein the second semi-static flip-flop controls the flow of the portion of the forward link data through the second operational sub-block.

21. The RFID tag of claim 20, wherein a first clock state duration of the second timing block clock signal is substantially the same as the first clock state duration of the timing block clock signal, and wherein a phase of the second timing block clock signal is not the same as a phase of the first timing block clock signal.

22. The RFID tag of claim 20, wherein a phase of the second timing block clock signal is substantially the same as a phase of the first timing block clock signal, and wherein a first clock state duration of the second timing block clock signal is not the same as the first clock state duration of the first timing block clock signal.

23. The RFID tag of claim 20, wherein a first clock state duration of the second timing block clock signal is not the same as the first clock state duration of the first timing block clock signal, and wherein a phase of the second timing block clock signal is not the same as a phase of the first timing block clock signal.

24. A method, including:

receiving a wireless signal at a radio frequency identification circuit; and

clocking a semi-static flip-flop included in the radio frequency identification circuit with a timing block clock signal having a first clock state duration shorter than a first dynamic storage time of the semi-static flip-flop and a second clock state duration longer than the first dynamic storage time, wherein a first static storage time of the semi-static flip-flop is longer then the first dynamic storage time.

25. The method of claim 24, further including:

detecting encoded symbols in the wireless signal; and

deriving the timing block clock signal from a frequency associated with the encoded symbols.

26. The method of claim 25, further including:

controlling the flow of the encoded symbols through an operational sub-block using the semi-static flip-flop.

27. The method of claim 24, further including:

deriving the timing block clock signal from a period of a high-frequency clock having a frequency higher than a frequency of the timing block clock signal.

28. The method of claim 24, further including:

deriving the timing block clock signal from forward link data.

29. The method of claim 24, in which the timing block clock signal has less than a 50% duty cycle.

30. An apparatus, including:

means for receiving a wireless signal at a radio frequency identification circuit; and

means for clocking a semi-static flip-flop included in the radio frequency identification circuit with a timing block clock signal having a first clock state duration shorter than a first dynamic storage time of the semi-static flip-flop and a second clock state duration longer than the first dynamic storage time, wherein a first static storage time of the semi-static flip-flop is longer then the first dynamic storage time.