Advanced seed layers for interconnects

• US 7,550,386 B2
• Filed: 10/05/2007
• Issued: 06/23/2009
• Est. Priority Date: 10/02/1999
• Status: Expired due to Term

• Current Assignee: Uri Cohen
• Original Assignee: Uri Cohen
• Inventors: Cohen, Uri
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US11/868,435
• Publication Number:
  US 20080026569A1
• Time in Patent Office: 627 Days
• Field of Search: 438/687, 257/E21.585
• US Class Current: 438/687
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers

Abstract

One embodiment of the present invention is a method for making metallic interconnects over a substrate, the substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the at least one opening has sidewalls and bottom and a width of less than about 0.13 μm, and the method includes: (a) depositing by a PVD technique a PVD seed layer over the substrate, said PVD seed layer being sufficiently thick over the field to enable uniform electroplating across the substrate; (b) depositing by a CVD technique a CVD seed layer over the PVD seed layer, wherein (i) the CVD seed layer having a thickness of less than about 150 Å over the field, (ii) the CVD seed layer is continuous over the sidewalls and bottom surfaces, (iii) at least one of the seed layers includes a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals, and (iv) the seed layers inside the at least one opening leave sufficient room for electroplating inside the at least one opening; and (c) filling the at least one opening by electroplating a metallic layer over the CVD seed layer, wherein the electroplated metallic layer includes a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals.

Claims

1. A method for depositing two or more seed layers suitable for electroplating metallic interconnects over a substrate, the substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the at least one opening and the field being ready for depositing one or more seed layers, the at least one opening having top corners, sidewalls, and bottom, and the method comprising:

depositing by a PVD technique a PVD seed layer over the substrate, said PVD seed layer being sufficiently thick over the field to enable uniform electroplating across the substrate, wherein said PVD seed layer has no substantial overhangs sealing or pinching-off the top corners of the at least one opening; and

depositing by a CVD technique a CVD seed layer over the PVD seed layer, wherein;

(i) the CVD seed layer having a thickness of less than about 300 Å

over the field, (ii) the CVD seed layer is continuous over the sidewalls and bottom surfaces, (iii) at least one of the seed layers comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals, and (iv) the seed layers inside the at least one opening leave sufficient room for electroplating inside the at least one opening.

2. The method of claim 1 wherein said substrate includes at least one barrier layer deposited over the field and inside surfaces of the at least one opening prior to the deposition of the PVD seed layer.

3. The method of claim 2 wherein the thickness of the PVD seed layer over the field is greater than about 1,500 Å

.

4. The method of claim 3 wherein the thickness of the CVD seed layer over the field is less than about 200 Å

.

5. The method of claim 1 wherein the at least one opening having a width of less than about 0.13 μ

m, and the CVD seed layer having a thickness of less than about 100 Å

over the field.

6. The method of claim 5 wherein the at least one opening having a width of less than about 0.10 μ

m.