Single poly CMOS imager
First Claim
1. A process for fabricating a semiconductor device comprising:
- forming a conductive layer over a substrate;
forming a resist layer directly on the conductive layer;
patterning the resist layer according to a desired arrangement of gates to be formed from the conductive layer, leaving a portion of the conductive layer exposed through the patterned resist layer;
partially etching the conductive layer using the patterned resist layer as masks to form a plurality of conductive structures, each conductive structure having a first width and being separated from each adjacent conductive structure by a first gap width;
removing remnants of the patterned resist layer, such that the plurality of conductive structures consist substantially entirely of conductive material from the conductive layer;
forming spacers on sidewalls of the conductive structures; and
etching the exposed conductive layer, such that the exposed conductive layer other than the plurality of conductive structures is substantially removed.
1 Assignment
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Accused Products
Abstract
More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.
21 Citations
10 Claims
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1. A process for fabricating a semiconductor device comprising:
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forming a conductive layer over a substrate; forming a resist layer directly on the conductive layer; patterning the resist layer according to a desired arrangement of gates to be formed from the conductive layer, leaving a portion of the conductive layer exposed through the patterned resist layer; partially etching the conductive layer using the patterned resist layer as masks to form a plurality of conductive structures, each conductive structure having a first width and being separated from each adjacent conductive structure by a first gap width; removing remnants of the patterned resist layer, such that the plurality of conductive structures consist substantially entirely of conductive material from the conductive layer; forming spacers on sidewalls of the conductive structures; and etching the exposed conductive layer, such that the exposed conductive layer other than the plurality of conductive structures is substantially removed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification