Semiconductor memory device

• US 7,561,464 B2
• Filed: 04/21/2008
• Issued: 07/14/2009
• Est. Priority Date: 07/25/2005
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Toda, Haruki
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US12/106,919
• Publication Number:
  US 20080198654A1
• Time in Patent Office: 449 Days
• Field of Search: 365/185.03, 365/185.17, 365/185.2, 365/185.23
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

A semiconductor memory device includes: first and second cell arrays each having a plurality of memory cells; and a sense amplifier circuit for reading out data of the first and second cell arrays, wherein plural information cells and at least one reference cell are set in each of the first and second cell arrays, one of four data levels L0, L1, L2 and L3 (where, L0<L1<L2<L3) being written into the information cell, reference level Lr (where, L0<Lr<L1) being written into the reference cell to used for detecting the data level of the information cell, and wherein the sense amplifier circuit detects a cell current difference between the information cell and the reference cell simultaneously selected from the first and second cell arrays.

Claims

1. A semiconductor memory device comprising:

first and second cell arrays each having a plurality of electrically rewritable memory cells arranged therein; and

a sense amplifier circuit configured to read out data of the first and second cell arrays,

wherein plural information cells are set in the first cell array, and at least one reference cell are set in the second cell array, one of four data levels L0, L1, L2 and L3 (where, L0<

L1<

L2<

L3<

) being written into an information cell, reference level Lr (where, L0<

Lr<

L1) being written into the reference cell to be used for detecting the data level of the information cell,

wherein the sense amplifier circuit is configured to detect a cell current difference between the information cell and the reference cell selected from the first and second cell arrays, respectively,

wherein the four data levels L0, L1, L2 and L3 of the information cell are threshold voltage levels with a relationship as follows;

L0 is an erase state with a certain threshold voltage; and

L1, L2 and L3 are write states with threshold voltages with a relationship of L1<

L3-L2, and L2-L1<

L3-L2,

and wherein the reference level Lr is a write state with a threshold voltage lower than L1.

2. The semiconductor memory device according to claim 1, wherein the information cell stores one of the four data levels L0, L1, L2 and L3 as a four-value data (HB,LB) where HB is a higher bit;

and LB is a lower bit.

3. The semiconductor memory device according to claim 2,

wherein the four-value data is read out with the following procedures of:

a first read procedure for applying a first read voltage and a reference voltage to a selected information cell and a selected reference cell, respectively, thereby reading out a higher bit, the first read voltage being equal to or nearly equal to the data level L2, the reference voltage being higher than the reference level Lr;

a second read procedure for applying a second read voltage and the reference voltage to the selected information cell and the selected reference cell, respectively, thereby reading out a lower bit when the higher bit is in a first logic state, the second read voltage being equal to or nearly equal to the data level L3; and

a third read procedure for applying a third read voltage and the reference voltage to the selected information cell and the selected reference cell, respectively, thereby reading out a lower bit when the higher bit is in a second logic state, the third read voltage being equal to or nearly equal to the data level L1.

4. The semiconductor memory device according to claim 3, wherein the lower bit is read out independently from the higher bit with judging whether the number of “

1”

data obtained through the second and third read procedures is even or odd.

5. The semiconductor memory device according to claim 2,

wherein the four-value data is written with the following procedures of:

a first write procedure for writing the reference level into the reference cell, which is in an erase state with the data level L0;

a second write procedure for selectively increasing the threshold voltage of the information cell, which is in the erase state with the data level L0, to the data level L2 based on the higher bit data;

a third write procedure for selectively increasing the threshold voltage of the information cell with the data level L2, to the data level L3 based on the higher bit data and the lower bit data; and

a fourth write procedure for selectively increasing the threshold voltage of the information cell, which is in the erase state with the data level L0, to the data level L1 based on the higher bit data and the lower bit data.

6. The semiconductor memory device according to claim 1, wherein the first and second cell arrays are disposed as sandwiching the sense amplifier circuit therebetween, each of the first and second cell arrays having NAND strings each having plural memory cells connected in series.

7. The semiconductor memory device according to claim 6, wherein each of the first and second cell arrays has plural blocks arranged in the direction of a bit line, each block being constituted by a set of NAND strings arranged in the direction of a word line, at least one block in each the first and second cell array being selected as a reference cell-use block while the remaining blocks being selected as information cell-use blocks;

and wherein the sense amplifier circuit has plural sense units each having a differential amplifier, which detects cell current difference between the information cell and the reference cell in the information cell-use block and the reference cell-use block, respectively, which are selected in one and the other of the first and second cell arrays, so as to sense data.

8. The semiconductor memory device according to claim 7,

wherein the sense unit further comprises:

a reference current source circuit selectively connected to one input node of the differential amplifier to supply a reference current to it for detecting a cell current input to the other input node;

two data latches disposed to be data-transferable between those and the differential amplifier, in which the higher bit data and the lower bit data are loaded, respectively; and

a bit line precharging circuit disposed in addition to the current source in the differential amplifier for precharging a selected bit line during a certain period prior to activation of the differential amplifier.

9. The semiconductor memory device according to claim 7, wherein at a data read time and an information cell'"'"'s write-verify time, the information cell is coupled to one bit line within a pair of bit lines selected in the first and second cell array while the reference cell is coupled to the other, the pair of bit lines being coupled to two input nodes of the differential amplifier.

10. The semiconductor memory device according to claim 7, wherein at a verify-erase time and a reference cell'"'"'s verify-write time, the first and second cell arrays are sequentially selected in accordance with the complementary data stored in two data latches, and when a bit line in a selected cell array at the verify-read time is coupled to one input node of the differential amplifier, the reference current source circuit is coupled to the other input node.

11. The semiconductor memory device according to claim 7, wherein at a data read time, it is judged whether the number of “

1”

read data is even or odd based on the data-transferring operation of a shift-register constituted by two data latches.

12. A semiconductor memory device comprising:

first and second cell arrays each having word lines and bit lines disposed in parallel and a plurality of electrically rewritable memory cells arranged therein, plural information cells and at least one reference cell being set in each of the first and second cell arrays, one of four data levels L0, L1, L2 and L3 (where, L0<

L1<

L2<

L3) being written into an information cell, a reference level Lr (where, L0<

Lr<

L1) being written into the reference cell to be used for detecting the data level of the information cell;

word line driver circuits configured to selectively drive word lines in the first and second cell arrays; and

a sense amplifier circuit connected to a pair of bit lines, to which the information cell and the reference cell selected from the first and second cell arrays, are coupled, so as to detect a cell current difference between the information cell and the reference cell, thereby reading out data of the information cell,

wherein each of the word line driver circuits has at least two driving modes with respect to driving plural word lines simultaneously selected at a data read time and applied with respectively predetermined word line voltages as follows;

a first driving mode for applying a first voltage necessary for data-sensing to a first word line from the beginning; and

a second driving mode for applying a third voltage higher than a second voltage necessary for data-sensing to a second word line, and then restoring the third voltage to the second voltage,

wherein the four data levels L0, L1, L2 and L3 of the information cell are threshold voltage levels with a relationship as follows;

L0 is an erase state with a certain threshold voltage; and

L1, L2 and L3 are write states with threshold voltages with a relationship of L1<

L3-L2, and L2-L1<

L3-L2,

and wherein the reference level Lr is a write state with a threshold voltage lower than L1.

13. The semiconductor memory device according to claim 12, wherein each of the information cell stores one of the four data levels L0, L1, L2 and L3 as a four-value data (HB,LB) where HB is a higher bit;

and LB a lower bit.

14. The semiconductor memory device according to claim 13, wherein the four-value data is read out with the following procedures of:

a first read procedure for applying a first read voltage and a reference voltage to a selected information cell and a selected reference cell, respectively, thereby reading out a higher bit, the first read voltage being equal to or nearly equal to the data level L2, the reference voltage being higher than the reference level Lr;

a second read procedure for applying a second read voltage and the reference voltage to the selected information cell and the selected reference cell, respectively, thereby reading out a lower bit when the higher bit is in a first logic state, the second read voltage being equal to or nearly equal to the data level L3; and

a third read procedure for applying a third read voltage and the reference voltage to the selected information cell and the selected reference cell, respectively, thereby reading out a lower bit when the higher bit is in a second logic state, the third read voltage being equal to or nearly equal to the data level L1.

15. The semiconductor memory device according to claim 14, wherein the lower bit is read out independently from the higher bit by judging whether the number of “

1”

data obtained through the second and third read procedures is even or odd.

16. The semiconductor memory device according to claim 13, wherein the four-value data is written with the following procedures of:

a first write procedure for writing the reference level into the reference cell, which is in an erase state with the data level L0;

a second write procedure for selectively increasing the threshold voltage of the information cell, which is in the erase state with the data level L0, to the data level L2 based on the higher bit data;

a third write procedure for selectively increasing the threshold voltage of the information cell with the data level L2, to the data level L3 based on the higher bit data and the lower bit data; and

a fourth write procedure for selectively increasing the threshold voltage of the information cell, which is in the erase state with the data level L0, to the data level L1 based on the higher bit data and the lower bit data.

17. The semiconductor memory device according to claim 12, wherein the first and second cell arrays are disposed as sandwiching the sense amplifier circuit therebetween, each of the first and second cell arrays having NAND strings each having plural memory cells connected in series.