DRAM controller for graphics processing operable to enable/disable burst transfer

• US 7,562,184 B2
• Filed: 12/29/2004
• Issued: 07/14/2009
• Est. Priority Date: 01/07/2004
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kurata, Kazushi, Henmi, Masanori
• Primary Examiner(s): Thai; Tuan V
• Assistant Examiner(s): Ayash; Marwan
• Application Number:
  US11/023,570
• Publication Number:
  US 20050152211A1
• Time in Patent Office: 1,658 Days
• Field of Search: None
• US Class Current: 711/105
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Abstract

An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Claims

1. A DRAM controller for controlling a plurality of DRAMs capable of burst transfers and having command-issuing interval restriction of a predetermined number of cycles, the plurality of DRAMs being independent from each other and each comprising a plurality of memory banks, comprising:

a plurality of signal lines capable of connecting the plurality of DRAMs; and

an interface unit which assigns to the DRAMs a frame-buffer area including a plurality of two-dimensionally arranged drawing blocks, and accesses the DRAMs in accordance with graphics processing,

wherein the interface unit;

assigns different ones of the DRAMs to neighboring ones of the drawing blocks at least in part of the frame-buffer area,

issues, when performing a processing across the neighboring drawing blocks to which the different DRAMs are assigned, active commands alternately in consecutive cycles or simultaneously to each of the different DRAMs, and

includes a burst transfer control unit for outputting individual signals to the DRAMs in order for stopping burst transfer of at least one of the plurality of DRAMs independently during burst transfer by another DRAMA,

wherein at least one of the plurality of signal lines is shared by the plurality of DRAMs and the at least one of the signal lines shared by the plurality of DRAMs includes data signal lines for transmitting data signals.

2. The controller of claim 1, wherein the DRAMs include first and second DRAMs, and

the interface unit assigns the first and second DRAMs to the drawing blocks in the frame- buffer area in a checkered pattern.

3. The controller of claim 1, wherein the interface unit includes an address control unit for outputting individual bank select signals and individual address signals to the DRAMs.

4. The controller of claim 3, wherein the interface unit assigns regions that have row addresses having a difference of 0 or 1 in the different DRAMs, to the neighboring drawing blocks at least in the part of the frame-buffer area, and

the address control unit outputs individual 0th bits of the address signals to the DRAMs, while outputting commonly remaining bits thereof to the DRAMs.

5. The controller of claim 1, wherein the interface unit includes a command control unit which is configured so as to be capable of issuing individual control commands to the DRAMs.

6. The controller of claim 5, wherein the command control unit is capable of issuing a read command or a write command to one of the DRAMs and issuing a precharge command to another one of the DRAMs, in a common cycle.

7. The controller of claim 6, wherein the command control unit is capable of outputting a precharge signal together with issuing the precharge command.

8. The controller of claim 1, wherein the interface unit includes a read control unit for controlling validity/invalidity of read data from the DRAMs individually such that read data from only one of the plurality of DRAM becomes active at a time.

10. A control method in the DRAM controller of claim 1, comprising:

a step in which the interface unit receives an instruction to perform graphics processing that extends across adjacent first and second drawing blocks to which first and second DRAMs included in the DRAMs have been respectively assigned;

a step in which in accordance with the instruction, the interface unit instructs the first DRAM to perform a burst write to or a burst read from an area corresponding to the first drawing block; and

a step in which in accordance with the instruction, the interface unit instructs the second DRAM to perform a burst write to or a burst read from an area corresponding to the second drawing block, while the burst transfer control unit outputs to the first DRAM the signal for stopping burst transfer.

12. The controller of claim 1, wherein the individual signals are individual clock enable signals, and the individual clock enable signals are input to the plurality of DRAMs using a part of the plurality of signal lines in order to stop burst transfer of each of the plurality of DRAMs independently.

13. The controller of claim 12, wherein burst tranfer of each DRAM is stopped by activating individual clock enable signal respectively.

9. A DRAM controller for controlling a plurality of DRAMs capable of burst transfers and having command-issuing interval restriction of a predetermined number of cycles, the plurality of DRAMs being independent from each other and each comprising a plurality of memory banks, comprising:

a plurality of signal lines capable of connecting the plurality of DRAMs; and

an interface unit which assigns each of a plurality of frame-buffer areas including a plurality of two-dimensionally arranged drawing blocks to any one of the DRAMs, and accesses the DRAMs in accordance with graphics processing,

wherein the interface unit;

assigns different ones of the DRAMs to the respective frame-buffer areas,

issues, when performing a processing across neighboring drawing blocks to which different DRAMs are assigned, active commands alternately in consecutive cycles or simultaneously to each of the different DRAMs, and

includes a burst transfer control unit for outputting individual signals to the DRAMs in order for stopping burst transfer of at least one of the plurality of DRAMs independently during burst transfer by another DRAMA

wherein at least one of the plurality of signal lines is shared by the plurality of DRAMs and the at least one of the signal lines shared by the plurality of DRAMs includes data signal lines for transmitting data signals.

11. A control method in the DRAM controller of claim 9, comprising:

A step in which the inteface unit receives an instruction to perform graphics processing using first and second frame-buffer areas assigned respectively to first and second DRAMs included in the DRAMs;

a step in which in accordance with the instruction, the interface unit instructs the first DRAM to perform a burst write to or a burst read from the first frame-buffer area; and

a step in which in accordance with the instruction, the interface unit instructs the second DRAM to perform a burst write to or a burst read from the second frame-buffer area, while the burst transfer control u nit outputs to the first DRAM the signal for stopping burst transfer.

14. The controller of claim 9, wherein the individual signals are individual clock enable signals, and the individual clock enable signals are input to the plurality of DRAMs using a part of the plurality of signal lines in order to stop burst transfer of each of the plurality of DRAMs independently.

15. The controller of claim 14, wherein the burst transfer of each DRAM is stopped by activating individual clock enable signal respectively.