Runtime configurable arithmetic and logic cell
First Claim
1. A Field Programmable Gate Array device that is configurable during runtime, comprising:
 a plurality of configurable cells that are configurable by configuration information;
a configurable interconnect structure adapted to transmit data in an at least twodimensional way, at least some of the plurality of configurable cells being configurable for connection to said interconnect structure, wherein said at least some configurable cells include units for arithmetic operations, at least one of the configurable cells that include units for arithmetic operations including;
an arithmetic operation unit, the arithmetic operation unit including a multiplier stage and an adder stage;
at least three inputs and at least one output for data;
at least three input registers;
at least one output register;
a return path; and
at least one multiplexer; and
an interconnection selection unit adapted to selectively interconnect said at least one of the configurable cells with others of the configurable cells;
wherein;
the at least three input registers and the at least one output register allow for decoupling of the at least three inputs and the at least one output from said interconnect by storing of operand inputs, the decoupling supporting at least one of pipelining and a decoupling during configuration;
said multiplier stage is connectable to;
(a) at least two of the input registers for receiving an input of two operands; and
(b) said adder stage, said connections to (a) and (b) being such that a selection can be made between at least two of;
(i) adding the two operand inputs;
(ii) adding an output of said multiplier stage and a further operand input;
(iii) adding the output of said multiplier stage and results of the at least one of the configurable cells; and
(iv) adding (a) one of the operand inputs and (b) at least one of the results of the at least one of the configurable cells;
said return path is adapted to return said results of said at least one of the configurable cells from the at least one output register as an operand via said at least one multiplexer, said at least one multiplexer selecting for further processing one of an external operand input and said results; and
said at least one multiplexer is arranged between at least one of said input registers and said adder stage so as to allow said at least one of the configurable cells to selectively have direct access to its own results which are returned as operands for calculations in a serial manner.
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Abstract
A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a powersaving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers.
526 Citations
19 Claims

1. A Field Programmable Gate Array device that is configurable during runtime, comprising:

a plurality of configurable cells that are configurable by configuration information; a configurable interconnect structure adapted to transmit data in an at least twodimensional way, at least some of the plurality of configurable cells being configurable for connection to said interconnect structure, wherein said at least some configurable cells include units for arithmetic operations, at least one of the configurable cells that include units for arithmetic operations including; an arithmetic operation unit, the arithmetic operation unit including a multiplier stage and an adder stage; at least three inputs and at least one output for data; at least three input registers; at least one output register; a return path; and at least one multiplexer; and an interconnection selection unit adapted to selectively interconnect said at least one of the configurable cells with others of the configurable cells; wherein; the at least three input registers and the at least one output register allow for decoupling of the at least three inputs and the at least one output from said interconnect by storing of operand inputs, the decoupling supporting at least one of pipelining and a decoupling during configuration; said multiplier stage is connectable to;
(a) at least two of the input registers for receiving an input of two operands; and
(b) said adder stage, said connections to (a) and (b) being such that a selection can be made between at least two of;(i) adding the two operand inputs; (ii) adding an output of said multiplier stage and a further operand input; (iii) adding the output of said multiplier stage and results of the at least one of the configurable cells; and (iv) adding (a) one of the operand inputs and (b) at least one of the results of the at least one of the configurable cells; said return path is adapted to return said results of said at least one of the configurable cells from the at least one output register as an operand via said at least one multiplexer, said at least one multiplexer selecting for further processing one of an external operand input and said results; and said at least one multiplexer is arranged between at least one of said input registers and said adder stage so as to allow said at least one of the configurable cells to selectively have direct access to its own results which are returned as operands for calculations in a serial manner.  View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)

1 Specification