Transceiver module and integrated circuit with multi-rate eye openers and bypass
First Claim
Patent Images
1. An integrated circuit for use in a transceiver module, the integrated circuit comprising:
- a first electrical input port for receiving a first serial electrical data stream;
receiver eye opener circuitry for retiming and reshaping the first serial electrical data stream;
a first electrical output port for transmitting the retimed and reshaped first serial electrical data stream to external to the integrated circuit;
receiver bypass circuitry for switchably selecting, based on a data rate of the first electrical data stream, a bypass data path from the first electrical input port to the first electrical output port to bypass retiming and reshaping of the first serial electrical data stream;
a second electrical input port for receiving a second serial electrical data stream from external to the integrated circuit;
transmitter eye opener circuitry for retiming and reshaping the second serial electrical data stream; and
a second electrical output port for transmitting the retimed and reshaped second serial electrical data stream.
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Abstract
A transceiver module having intergrated eye diagram opening functionality for reducing jitter is describe. The transceiver module may transmitter eye opener and a receiver eye opener integrated in a single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modes, bypass features, bit error rate testing, and power down mode.
175 Citations
29 Claims
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1. An integrated circuit for use in a transceiver module, the integrated circuit comprising:
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a first electrical input port for receiving a first serial electrical data stream; receiver eye opener circuitry for retiming and reshaping the first serial electrical data stream; a first electrical output port for transmitting the retimed and reshaped first serial electrical data stream to external to the integrated circuit; receiver bypass circuitry for switchably selecting, based on a data rate of the first electrical data stream, a bypass data path from the first electrical input port to the first electrical output port to bypass retiming and reshaping of the first serial electrical data stream; a second electrical input port for receiving a second serial electrical data stream from external to the integrated circuit; transmitter eye opener circuitry for retiming and reshaping the second serial electrical data stream; and a second electrical output port for transmitting the retimed and reshaped second serial electrical data stream. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. In an integrated circuit for use in a transceiver module, a method of communicating data comprising, within the integrated circuit:
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receiving a first serial electrical data stream; switchably selecting or not selecting a bypass data path based on a data rate of the first electrical data stream; retiming and reshaping the first serial electrical data stream when the bypass data path is not selected; passing through the first serial electrical data stream when the bypass data path is selected; transmitting the retimed and reshaped first serial electrical data stream to external to the integrated circuit when the bypass data path is not selected, or transmitting the passed-through first serial electrical data stream to external to the integrated circuit when the bypass data path is selected; receiving a second serial electrical data stream from external to the integrated circuit; retiming and reshaping the second serial electrical data stream; and transmitting the retimed and reshaped second serial electrical data stream. - View Dependent Claims (9, 10)
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11. A transceiver module, comprising:
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a ROSA; a TOSA; receive path eye opener circuitry including a first input and output and configured so that a first data stream received from the ROSA has a lower jitter at the first output than at the first input; receive path bypass circuitry configured so that when the first data stream has a data rate less than about 10 Gb/s, the first data stream bypasses the receive path eye opener circuitry along a first bypass path; transmit path eye opener circuitry including a second input and output and configured so that a second data stream has a lower jitter at the second output than at the second input; and transmit path bypass circuitry configured so that when the second data stream has a data rate less than about 10 Gb/s, the second data stream bypasses the transmit path eye opener circuitry along a second bypass path, the second bypass path being in communication with the TOSA. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A transceiver module, comprising:
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a ROSA; a TOSA; receive path eye opener circuitry including a first input and output and configured so that a first serial data stream received from the ROSA has a lower jitter at the first output than at the first input; receive path bypass circuitry configured so that when the first serial electrical data stream has a data rate below a predetermined threshold, the first serial data stream bypasses the receive path eye opener circuitry along a first bypass path; transmit path eye opener circuitry including a second input and output and configured so that a second serial data stream has a lower jitter at the second output than at the second input; and transmit path bypass circuitry configured so that when the second serial data stream has a data rate below a predetermined threshold, the second serial data stream bypasses the transmit path eye opener circuitry along a second bypass path, the second bypass path being in communication with the TOSA, and the transceiver module being substantially compliant with a XFP MSA. - View Dependent Claims (23, 24)
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25. A transceiver module, comprising:
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a ROSA and a TOSA; and a first IC configured to communicate with the ROSA, and a second IC configured to communicate with the TOSA, each IC configured to bypass clock and data recovery and retiming for a data rate of about 8.5 Gb/s, and comprising; a first buffer including a reference clock input and output; a second buffer including data signal input and output, and an LOS output; a CDR including; a data signal input and output, the CDR data signal input connected to the second buffer data signal output; reference clock input and output, the CDR reference clock input being connected to the first buffer reference clock output; and an LOL output; an RT including; a reference clock input connected to the CDR reference clock output; a data signal input connected to the CDR data signal output; and a data signal output; a multiplexer including; a first input connected to the data signal output of the second buffer; a second input connected to the RT data signal output; a third input; and an output; a third buffer including; an input connected to the multiplexer output; and an output; and a control logic module including; a first input connected to the LOS output; a second input connected to the LOL output; a third input connectible to an external device; a first output connectible to an external device; and a second output connected to the third input of the multiplexer. - View Dependent Claims (26, 27, 28, 29)
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Specification