Method and apparatus for a clock and data recovery circuit

• US 7,568,137 B1
• Filed: 03/27/2007
• Issued: 07/28/2009
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Kellermann, Martin Johann
• Primary Examiner(s): Kerveros; James C
• Application Number:
  US11/729,205
• Time in Patent Office: 854 Days
• Field of Search: 714/725
• US Class Current: 714/725
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

A method and apparatus for a clock and data recovery circuit that includes a set of serializer/deserializer (SERDES) circuits that are adapted to sample progressively delayed versions of an input data stream. The sampling rate is slightly higher than the data rate of the input data stream, which produces duplicate bits in the detected data stream. Error and offset matrices are used to generate an index pointer into a detected data matrix to extract the correct data bits from the duplicate bits of the detected data matrix. Down-sampling of the corrected data is performed to populate a ring buffer. Data is then extracted from the ring buffer using a clock signal whose frequency is adapted from the sampling clock signal used by the SERDES to prevent underflow/overflow of the ring buffer.

Claims

1. A clock and data recovery circuit, comprising:

a plurality of receiver segments coupled to receive an input data stream, wherein each receiver segment includes a plurality of deserializers adapted to sample programmably delayed representations of the input data stream to generate a plurality of data words; and

an error correction block coupled to receive the plurality of data words and adapted to remove duplicative data from the plurality of data words and merge each of the plurality of data words into detected data words.

2. The clock and data recovery circuit of claim 1, wherein each of the plurality of receiver segments comprises:

a first data path comprising a first delay block adapted to delay the input data stream by a first programmable delay amount to generate a first delayed data stream; and

a second data path comprising a second delay block adapted to delay the input data stream by a second programmable delay amount to generate a second delayed data stream.

3. The clock and data recovery circuit of claim 2, wherein the first data path further comprises a first deserialization block adapted to sample the first delayed data stream to generate first data words.

4. The clock and data recovery circuit of claim 3, wherein the second data path further comprises:

a second deserialization block adapted to sample the second delayed data stream to generate second data words; and

an inverter coupled to receive the second data words and adapted to generate inverted data words.

5. The clock and data recovery circuit of claim 4, wherein each of the plurality of receiver segments further comprises a logic gate coupled to receive the first data words and the inverted data words and adapted to generate error data words.

6. The clock and data recovery circuit of claim 5, wherein each of the plurality of receiver segments further comprises a bit mask generator coupled to receive the error data words and adapted to generate bit masks in response to the error data words.

7. The clock and data recovery circuit of claim 6, wherein each of the plurality of receiver segments further comprises a first error detector coupled to receive the first data words and the bit masks and adapted to detect errors in the first data words.

8. The clock and data recovery circuit of claim 7, wherein each of the plurality of receiver segments further comprise a second error detector coupled to receive the inverted data words and the bit masks and adapted to detect errors in the second data words.

9. The clock and data recovery circuit of claim 8, further comprising an error correction block adapted to receive detected errors from the first and second error detectors of each of the plurality of receiver segments and adapted to provide the detected data words, the detected data words being void of the detected errors.

10. A method of recovering data signals from an input data stream having a data rate, comprising:

generating a plurality of data word streams from data samples taken from a plurality of data bit streams, each data bit stream exhibiting a different delay in relation to the input data stream;

detecting error bits within the plurality of data words;

extracting data bits from the plurality of data words, the extracted data bits being void of the detected error bits; and

down-sampling the extracted data bits to recover the data signals from the input data stream.

11. The method of claim 10, wherein generating a plurality of data words comprises sampling each data bit stream using a sampling frequency that is less than twice the data rate.

12. The method of claim 10, wherein detecting error bits within the plurality of data words comprises:

populating detected data matrices with the plurality of data word streams;

detecting errors in the plurality of data word streams; and

populating error matrices with the detected errors, wherein each location of each error matrix is indicative of a potential error in a corresponding location of each detected data matrix.

13. The method of claim 12, wherein detecting errors comprises:

performing a logic function on selected data word stream pairs to generate an error word stream;

generating bit masks from the error word stream; and

performing a logic function with the bit masks and the selected data word stream pairs to detect duplicate data bits in the detected data matrices.

14. The method of claim 12, wherein extracting data bits comprises:

comparing the detected errors within the error matrices to a set of observed rules; and

correcting the detected errors within the error matrices in accordance with the observed rules.

15. The method of claim 14, wherein extracting data bits further comprises:

populating offset matrices with data that corresponds to the corrected error matrices;

generating an index pointer from data contained within the offset matrices;

addressing locations within the detected data matrices using the index pointer; and

copying data from each addressed location of the detected data matrices to a corresponding location within extracted data matrices.

16. The method of claim 15, wherein down-sampling the extracted data bits comprises:

extracting data from each column of the extracted data matrices;

performing a majority vote on the extracted column data; and

forming detected data words from a plurality of majority votes.

17. In a programmable logic device, a method of recovering data signals from an input data stream comprises:

receiving the input data stream using input/output pins of the programmable logic device;

routing the input data stream to a plurality of receiver segments associated with the input/output pins;

delaying the input data stream in each receiver segment using a programmable delay for each receiver segment;

generating a plurality of data words from data samples taken from the delayed data streams in each receiver segment;

extracting non-duplicative data bits from the plurality of data words; and

down-sampling the extracted data bits to recover the data signals from the input data stream.

18. The method of claim 17, wherein extracting non-duplicative data bits comprises:

populating detected data matrices with the plurality of data words;

detecting errors in the plurality of data words; and

populating error matrices with the detected errors, wherein each location of each error matrix is indicative of a potential error in a corresponding location of each detected data matrix.

19. The method of claim 18, wherein extracting non-duplicative data bits further comprises:

populating offset matrices with data that corresponds to the error matrices;

generating an index pointer from data contained within the offset matrices;

addressing locations within the detected data matrices using the index pointer; and

copying data from each addressed location of the detected data matrices to a corresponding location within extracted data matrices.

20. The method of claim 19, wherein down-sampling the extracted data bits comprises:

extracting data from each column of the extracted data matrices;

performing a majority vote on the extracted column data; and

forming the recovered data signals from a plurality of majority votes.