Methods and systems for designing high resolution analog to digital converters

• US 7,570,191 B2
• Filed: 06/10/2007
• Issued: 08/04/2009
• Est. Priority Date: 06/09/2006
• Status: Active Grant

• Current Assignee: Cosmic Circuits Private Limited
• Original Assignee: Cosmic Circuits Private Limited
• Inventors: Srinivasa Shetty, Venkatesh Teeka, Easwaran, Prakash, Kali Bhattacharya, Prasun
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US11/760,778
• Publication Number:
  US 20070285298A1
• Time in Patent Office: 786 Days
• Field of Search: 341/155, 341/156, 341/161, 341/120
• US Class Current: 341/161
• CPC Class Codes: H03M 1/0604 at one point, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/168 and delivering the same number of bits

Abstract

Methods and systems for designing a high resolution analog to digital converter (ADC) by eliminating the errors in the ADC stages. An error correction architecture and method eliminate the gain error and settling error of the residue amplifier in a pipelined ADC stage. A reference voltage error correction architecture and method eliminate the reference voltage error due to the sampling action in the ADC. The gain error correction method calculates the gain error using an error amplifier and eliminates the gain error at a later stage of the ADC. The reference voltage error correction method calculates the reference voltage error using an ideal reference voltage and corrects the error at a later stage of the ADC. Therefore, the constraints of gain and settling of the residue amplifier is significantly reduced.

Claims

1. A method comprising:

estimating an error in a residue amplifier in a first stage of a plurality of stages in an analog to digital converter (ADC), wherein said estimating comprising;

dividing an output signal of said first stage by a desired gain of the residue amplifier of the first stage using an attenuator to generate a modified output signal;

adding a digital to analog converter (DAC) value to said modified output signal to generate a reconstructed input signal; and

subtracting said reconstructed input signal from an input signal to the first stage for calculating a difference value between a desired output and an actual output, wherein said difference value includes said error;

providing the error estimated to a second stage of said plurality of stages through an error amplifier after multiplying the error with said desired gain; and

eliminating the error in said residue amplifier by adding the error to a residue value input to said second stage.

2. The method of claim 1 further comprising:

holding the error estimated in a sampling capacitor of the first stage.

3. The method of claim 1, wherein the closed loop gain of said error amplifier is equal to the product of closed loop gains of the residue amplifiers of the first stage and the second stage.

4. The method of claim 1, wherein said providing the error calculated further comprising:

multiplying the error with the closed loop gains of a set of residue amplifiers of successive stages before a particular stage; and

providing the error to said particular stage.

5. The method of claim 1, wherein the error comprises gain error and settling error in the analog to digital converter.

6. The method of claim 1, whereby the error in the residue amplifier is corrected in analog domain.

7. The method of claim 1, wherein the analog to digital converter is a pipelined analog to digital converter.

8. An analog to digital converter including a plurality of stages, each of said stages comprising a residue amplifier, said analog to digital converter comprising:

an attenuator for dividing an output signal of a first stage by a desired gain of said residue amplifier of said first stage to generate a modified output signal;

means for adding a digital to analog converter (DAC) value to said modified output signal to generate a reconstructed input signal;

means for subtracting said reconstructed input signal from an input signal to the first stage for calculating a difference value between a desired output and actual output, wherein said difference value includes said error;

a sampling capacitor for holding the error calculated in the first stage;

an error amplifier for providing the error calculated to a second stage of said plurality of stages after multiplying the error with said desired gain; and

means for adding the error to a residue value input to said second stage whereby correcting the error in the residue amplifier.

9. The analog to digital converter of claim 8, wherein the closed loop gain of said error amplifier is equal to the product of closed loop gains of the residue amplifiers of the first stage and the second stage.

10. The analog to digital converter of claim 8, further comprising:

means for multiplying the error with the closed loop gains of the residue amplifiers of successive stages before a particular stage; and

means for providing the error to said particular stage.

11. The analog to digital converter of claim 8, wherein said error comprises gain error and settling error in the analog to digital converter.

12. The analog to digital converter of claim 8, wherein the analog to digital converter is a pipelined analog to digital converter.

13. A method comprising:

calculating a reference voltage error in a first stage of a plurality of stages in an analog to digital converter, said calculating comprising;

estimating a difference value between a reference voltage provided to said first stage and an ideal reference voltage; and

multiplying said difference value with a closed loop gain of a residue amplifier of the first stage to calculate said reference voltage error;

providing the reference voltage error calculated to a second stage of the plurality of stages after multiplying the error with a closed loop gain of the residue amplifier of said second stage; and

eliminating the reference voltage error by adding the error to a residue value input to the second stage.

14. The method of claim 13, wherein said providing the reference voltage error comprising:

multiplying the reference voltage error with the closed loop gains of a set of residue amplifiers of successive stages before a particular stage; and

providing the reference voltage error to said particular stage.

15. An analog to digital converter including a plurality of stages comprising:

means for estimating a difference value between a reference voltage provided to a first stage of said plurality of stages and an ideal reference voltage;

means for multiplying said difference value with a closed loop gain of a residue amplifier of said first stage to calculate a reference voltage error;

means for providing said reference voltage error calculated to a second stage of the plurality of stages after multiplying the reference voltage error with a closed loop gain of the residue amplifier of said second stage; and

means for eliminating the reference voltage error by adding the error to a residue value input to the second stage.

16. The analog to digital converter of claim 15, further comprising:

means for multiplying the error with the closed loop gain of the residue amplifiers of successive stages before a particular stage; and

means for providing the error to said particular stage.

17. A method comprising:

calculating a reference voltage error in a first stage of a plurality of stages in an analog to digital converter, said calculating comprising;

estimating a difference value between a reference voltage provided to said first stage and an ideal reference voltage;

multiplying said difference value with a closed loop gain of a residue amplifier of the first stage to calculate said reference voltage error, wherein said difference value includes the reference voltage error;

digitizing the reference voltage error calculated using a digital logic after multiplying the reference voltage error with a closed loop gain of the residue amplifier of said second stage;

digitizing a residue value input to the second stage using an auxiliary analog to digital converter; and

adding the digitized reference voltage error with the digitized residue value input using an error correction logic, thereby eliminating the reference voltage error.

18. The method of claim 17, further comprising:

multiplying the digitized reference voltage error with the closed loop gain of the residue amplifiers of successive stages before a particular stage; and

providing the digitized reference voltage error to said particular stage.

19. The method of claim 17, wherein the analog to digital converter is a pipelined analog to digital converter.

20. The method of claim 17, whereby the reference voltage error in the residue amplifier is eliminated in digital domain.