Analog to digital converter with low power control

• US 7,573,416 B1
• Filed: 04/30/2008
• Issued: 08/11/2009
• Est. Priority Date: 04/30/2008
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Hathaway, Edward J., Richard, Jayme W., Ren, Juxiang
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US12/112,060
• Time in Patent Office: 468 Days
• Field of Search: 341/155, 341/158, 341/154
• US Class Current: 341/155
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

A circuit comprises a reference voltage generating circuit, a first switch, a second switch, and a capacitive element. The reference voltage generating circuit has an input and output terminal for providing a reference voltage. The first switch has a first terminal coupled to a first power supply voltage terminal, a second terminal coupled to the input terminal of the reference voltage generating circuit, and a control terminal for receiving a first control signal. The second switch has a first terminal coupled to the output terminal of the reference voltage generating circuit, a second terminal, and a control terminal for receiving a second control signal. The capacitive element has a first plate electrode coupled to the second terminal of the second switch, and a second plate electrode coupled to a second power supply voltage terminal.

Claims

1. A circuit comprising:

a reference voltage generating circuit having an input and an output terminal for providing a reference voltage;

a first switch having a first terminal coupled to a first power supply voltage terminal, a second terminal coupled to the input and the output terminal of the reference voltage generating circuit, and a control terminal for receiving a first control signal;

a second switch having a first terminal coupled to the input and the output terminal of the reference voltage generating circuit, a second terminal, and a control terminal for receiving a second control signal; and

a capacitive element having a first plate electrode coupled to the second terminal of the second switch, and a second plate electrode coupled to a second power supply voltage terminal.

2. The circuit of claim 1, wherein the first control signal is characterized as being a low power mode signal provided by a processor.

3. The circuit of claim 1 further comprising an analog-to-digital converter having a reference voltage input terminal for receiving at least one reference voltage from the reference voltage generating circuit.

4. The circuit of claim 3, wherein the analog-to-digital converter is characterized as being a redundant signed division analog-to-digital converter.

5. The circuit of claim 1, wherein the reference voltage generating circuit comprises a plurality of series-connected resistive elements.

6. The circuit of claim 1 further comprising a precharge circuit coupled to the first terminal of the second switch, the precharge circuit for precharging the capacitive element to a predetermined voltage in response to a mode control signal.

7. The circuit of claim 1, wherein the second control signal is provided in response to setting a register bit field of a processor.

8. The circuit of claim 1, wherein the circuit is implemented as a portion of an integrated circuit and the capacitive element is external to the integrated circuit.

9. The circuit of claim 1, wherein the second control signal is characterized as being an active mode control signal.

10. A circuit comprising:

a voltage divider comprising a plurality of series-connected resistive elements;

a first switch having a first terminal coupled to a first power supply voltage terminal, a second terminal coupled to the plurality of series-connected resistive elements, and a control terminal for receiving a first control signal;

a second switch having a first terminal coupled to the plurality of resistive elements, a second terminal, and a control terminal for receiving a second control signal; and

a capacitive element having a first plate electrode coupled to the second terminal of the second switch, and a second plate electrode coupled to a second power supply voltage terminal.

11. The circuit of claim 10, wherein the second control signal is provided in response to setting a register bit field of a processor.

12. The circuit of claim 10, wherein the voltage divider is for providing a reference voltage for use by an analog-to-digital converter.

13. The circuit of claim 10, wherein the circuit is formed on an integrated circuit and the capacitive element is external to the integrated circuit.

14. The circuit of claim 10, wherein the first and second switches are implemented as P-channel transistors.

15. The circuit of claim 10, wherein the plurality of series-connected resistive elements comprises:

a first resistive element having a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to the first terminal of the second switch;

a second resistive element having a first terminal coupled to the second terminal of the first resistive element, and a second terminal;

a third resistive element having a first terminal coupled to the second terminal of the second resistive element, and a second terminal; and

a fourth resistive element having a first terminal coupled to the second terminal of the third resistive element, and a second terminal coupled to the second power supply voltage terminal.

16. The circuit of claim 10 further comprising a precharge circuit coupled to the first terminal of the second switch, the precharge circuit for precharging the capacitive element to a predetermined voltage in response to a mode control signal.

17. A method comprising:

determining that a circuit is needed to perform a first task requiring a first accuracy;

causing a reference voltage generating circuit to operate in an active mode;

providing a power supply voltage to the reference voltage generating circuit;

coupling a capacitor to the reference voltage generating circuit;

providing a reference voltage having the first accuracy from the reference voltage generating circuit to the circuit;

determining that the circuit is to operate in a low power mode;

causing the reference voltage generating circuit to enter the low power mode;

decoupling the power supply voltage from the reference voltage generating circuit;

decoupling the capacitor from the reference voltage generating circuit;

determining that the circuit is needed for a second task requiring a second accuracy, the second accuracy being less than the first accuracy;

providing the power supply voltage to the reference voltage generating circuit;

causing the reference voltage generating circuit to operate in a low accuracy active mode; and

performing the second task at the second accuracy with the capacitor decoupled from the reference voltage generating circuit in the low accuracy active mode.

18. The method of claim 17, wherein providing a reference voltage having the first accuracy further comprises waiting a predetermined time period for the capacitor to fully charge.

19. The method of claim 17, wherein determining that a circuit is needed further comprises determining that an analog-to-digital converter circuit is needed.

20. The method of claim 17, wherein coupling a capacitor to the reference voltage generating circuit further comprises setting a control bit in a processor.