Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine

• US 7,574,584 B2
• Filed: 07/21/2005
• Issued: 08/11/2009
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauvel, Gerard, Kuusela, Maija
• Primary Examiner(s): Huisman; David J
• Application Number:
  US11/186,239
• Publication Number:
  US 20060026393A1
• Time in Patent Office: 1,482 Days
• Field of Search: 708/490, 708/495, 708/497, 708/498, 708/503, 708/505, 708/508, 708/204, 712/221, 712/222
• US Class Current: 712/222
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In some embodiments, a processor includes fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to software and partly in the hardware state machine. For a floating point add instruction, mantissa addition is executed in the integer pipeline and the plurality of operations performed by the hardware state machine includes testing of exponents, testing for overflow and underflow conditions, packing, and rounding detection.

Claims

1. A processor, comprising:

fetch logic that fetches instructions;

a hardware stack;

an integer pipeline; and

a hardware state machine that is separate from and interacts with the integer pipeline,

wherein a floating point instruction in the instructions is executed by coordinating execution of a sequence of software instructions in the integer pipeline with a plurality of operations performed by the hardware state machine, wherein the coordinating includes sharing intermediate results between the plurality of operations and the sequence of software instructions on the hardware stack, wherein the floating point instruction is a floating point add instruction, and wherein mantissa addition is executed in the integer pipeline and the plurality of operations performed by the hardware state machine includes testing of exponents, testing for overflow and underflow conditions, packing, and rounding detection.

2. The processor of claim 1, wherein the sequence of software instructions is initiated by decoding the floating point instruction.

3. The processor of claim 1, wherein the coordinating further includes passing one or more intermediate results between the integer pipeline and the hardware state machine via by-passes or a register file.

4. The processor of claim 1, wherein the plurality of operations performed by the hardware state machine includes at least one operation selected from a group consisting of extracting bit fields from input floating point values, testing the extracted bit fields for predetermined cases, rounding, and packing.

5. The processor of claim 1, wherein another instruction is a floating point instruction selected from a group consisting of a floating point multiply instruction, a floating point-to-integer conversion instruction, an integer-to- floating point conversion instruction, and a floating point compare instruction.

6. The processor of claim 1, wherein another instruction is a floating point multiply instruction, and wherein mantissa multiplication is executed in the integer pipeline, and the plurality of operations performed by the hardware state machine includes testing of exponents, testing for overflow and underflow conditions, packing, and rounding detection.

7. The processor of claim 1, wherein another instruction is an integer-to-floating point conversion instruction, and wherein mantissa shifting is executed in the integer pipeline, and wherein the plurality of operations performed by the hardware state machine includes determining the needed shift from an exponent, and rounding detection.

8. The processor of claim 1, wherein another instruction is a floating point compare instruction, and wherein integer comparisons are executed in the integer pipeline, and the plurality of operations performed by the hardware state machine includes testing for special values.

9. The processor of claim 1, wherein the processor is included in a cellular telephone.

10. The processor of claim 1, wherein the processor is coupled to an antenna.

11. The processor of claim 1, wherein another instruction is a floating point-to-integer conversion instruction, and wherein mantissa shifting is executed in the integer pipeline, and the plurality of operations performed by the hardware state machine includes testing of exponents.

12. A method, comprising:

fetching a floating point instruction; and

executing the floating point instruction by coordinating execution of a sequence of software instructions in an integer pipeline with a plurality of operations performed by a hardware state machine, wherein the coordinating includes sharing intermediate results between the plurality of operations and the sequence of software instructions on a hardware stack, wherein the floating point instruction is a floating point add instruction, and wherein mantissa addition is executed in the integer pipeline, and the plurality of operations performed by the hardware state machine comprises testing for overflow and underflow conditions, packing, and rounding detection.

13. The method of claim 12, wherein another instruction is an instruction selected from a group consisting of a floating point multiply instruction, a floating point-to-integer conversion instruction, an integer-to-floating point conversion instruction, and a floating point compare instruction.

14. The method of claim 12, wherein the plurality of operations performed by the hardware state machine includes at least one operation selected from a group consisting of extracting bit fields from input floating point values, testing the extracted bit fields for predetermined cases, rounding, and packing.

15. The method of claim 12, wherein another instruction is a floating point multiply instruction, and wherein mantissa multiplication is executed in the integer pipeline, and the plurality of operations performed by the hardware state machine includes testing for overflow and underflow conditions, packing, and rounding detection.

16. The method of claim 12, wherein another instruction is an integer-to-floating point conversion instruction, and wherein mantissa shifting is executed in the integer pipeline, and the plurality of operations performed by the hardware state machine includes determining the needed shift from an exponent and rounding detection.

17. The method of claim 12, wherein another instruction is a floating point compare instruction, and wherein integer comparisons are executed in the integer pipeline, and the plurality of operations performed by the hardware state machine includes testing for special values.

18. The method of claim 12,wherein another instruction is a floating point-to-integer conversion instruction, and wherein mantissa shifting is executed in the integer pipeline, and the plurality of operations performed by the hardware state machine includes testing of exponents.