Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC)

• US 7,576,668 B2
• Filed: 11/02/2007
• Issued: 08/18/2009
• Est. Priority Date: 07/13/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Oswal, Sandeep, Sinha, Vikas Kumar, Agarwal, Nitin, Pentakota, Visvesvararaya A., Udupa, Anand Hariraj
• Primary Examiner(s): Nguyen; Linh V
• Application Number:
  US11/934,611
• Publication Number:
  US 20080055129A1
• Time in Patent Office: 655 Days
• Field of Search: 341/118, 341/120, 341/122, 341/155, 341/161, 341/162
• US Class Current: 341/122
• CPC Class Codes: H03M 1/168 and delivering the same number of bits

Abstract

A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Claims

1. An analog to digital converter (ADC) comprising:

a first sample and hold amplifier (SHA) receiving an input signal and providing an amplified version of the input signal on a first path;

a second SHA receiving the input signal and also providing an amplified version of the input signal on a second path;

a stage of an ADC generating a sub-code from the input signal, the stage including;

a flash ADC sampling the input signal on the first path from the first SHA, and generating a sub-code representing a strength of the input signal; and

a DAC-Subtractor circuit sampling the input signal on the second path from the second SHA, the first circuit generating an amplified residue signal for processing by a next stage that forms at least a portion of the ADC.

2. The ADC of claim 1, wherein flash ADC determines the sub-code in a decision duration which overlaps with a duration in which the DAC-Subtractor circuit performs the sampling.

3. The ADC of claim 2, wherein flash ADC generates the sub-code before the DAC-Subtractor circuit completes sampling the input signal on the second path.

4. A device comprising:

a processor processing a plurality of digital values; and

an ADC to generate said plurality of digital values, the ADC including;

a first SHA receiving the input signal and providing an amplified version of input signal on a first path;

a second SHA receiving the input signal and also providing an amplified version of the input signal on a second path;

a flash ADC sampling the input signal on the first path from the first SHA, and generating a sub-code representing a strength of the input signal; and

a the DAC-Subtractor circuit sampling the input signal on the second path from the second SHA, the quantizer and the first circuit being at least a portion of a stage of the ADC, the first circuit generating an amplified residue signal for processing by a next stage that forms at least a portion of the ADC.

5. The device of claim 4, wherein the strength comprises a voltage level.

6. The device of claim 4, wherein the flash ADC samples the input signal for a first duration and the DAC-Subtractor circuit samples the input signal for a second duration, wherein the first duration is less than the second duration.

7. The device of claim 6, wherein the flash ADC determines said sub-code in a decision duration which overlaps with the second duration.

8. The device of claim 6, wherein the DAC-Subtractor circuit comprises a plurality of capacitors, a plurality of switches and an amplifier together sampling the input signal and amplifying a difference of the strength and a voltage equivalent of the sub-code to generate the amplified residue signal.

9. A method of generating a sub-code from an input signal using a stage of an ADC, said method comprising:

amplifying the input signal using a first amplifier and a second amplifier, wherein the first and second amplifiers are separate amplifiers;

providing an output of the first amplifier on a first path to a flash ADC;

providing an output of the second amplifier on a second path to a DAC-Subtractor circuit;

generating a sub-code by the flash ADC based at least in part on a signal received on the first path from the first amplifier; and

generating an amplified residue signal for processing by a next stage based on a signal received by the DAC-Subtractor circuit on the second path from the second amplifier, wherein the next stage forms at least a portion of the ADC.