Method and system for multiple tuner application using a low noise broadband distribution amplifier

• US 7,579,912 B2
• Filed: 08/08/2002
• Issued: 08/25/2009
• Est. Priority Date: 08/15/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: McMullin, Donald, Dauphinee, Leonard, Burns, Lawrence M, Fanous, Adel
• Primary Examiner(s): NGUYEN, SIMON
• Application Number:
  US10/214,097
• Publication Number:
  US 20030035070A1
• Time in Patent Office: 2,574 Days
• Field of Search: 455/191.1, 455/295, 4552321-2532, 455324-325, 455/333, 455/340, 455303-306, 330/124.R, 330/278, 330/254, 330/295
• US Class Current: 330/254
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2203/45302 the common gate stage of a cascode dif amp being controlled
• CPC Class Codes: H03F 2203/45311 the common gate stage of a cascode dif amp being implemented by multiple transistors
• CPC Class Codes: H03F 2203/45464 the CSC comprising one or more coils
• CPC Class Codes: H03F 2203/45466 the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45696 the LC comprising more than two resistors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45201 Non-folded cascode stages
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence

Abstract

An active splitter circuit arrangement includes a first amplification module having a number of first input ports and first output ports. The first amplification module is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals, each substantially matching the input signal. Also included is a first gain control device having a number of gain input ports respectively coupled to the first output ports and a gain output port coupled to at least one of the first input ports. The first gain control device is configured to control a gain of the first amplification module. Next, a number of second amplification modules corresponding to the number of output signals has a number of second input ports respectively coupled to the first output ports. Each second amplification module is configured to receive a control signal from the second gain control device, provide second stage amplification to a corresponding one of the number of output signals based upon the control signal and produce an amplified output signal.

Claims

1. A circuit comprising:

a differential signal splitting mechanism configured to (i) receive a first differential signal as an input, (ii) amplify the received first differential signal, (iii) produce from the amplified first differential signal a number of second differential signals, each being substantially identical to the amplified first differential signal, and (iv) output each of the amplified second differential signals; and

a number of tuners corresponding to the number of second differential signals, each tuner being configured to receive one of the second differential signals output from the differential signal splitting mechanism and derive one or more informational differential signals therefrom.

2. The circuit of claim 1, wherein each of the number of tuners excludes a low noise amplification function.

3. The circuit of claim 1, further comprising a variable gain amplifier coupled to an input of the signal splitting mechanism, the variable gain amplifier being configured to receive the first differential signal as an input thereto.

4. The circuit of claim 1, further comprising differential transmission lines to couple the signal splitting mechanism to the number of tuners.

5. The circuit of claim 1, wherein the signal splitting mechanism is an active signal splitting mechanism.

6. The circuit of claim 1, wherein the circuit is a cable set-top box configured for use in at least one of a television, a cable modem, a personal video recorder, and an out of band device.

7. A method of amplifying a differential signal in a device including a first amplification module, a number of second amplification modules, and a gain control device, the method comprising:

receiving a transmitted differential signal in the first amplification module and applying a first level of amplification thereto; and

providing the first level amplified signal to each of the number of second amplification modules to produce a corresponding number of second level amplified differential signals, each second level amplified differential signal having characteristics substantially similar to the other of the number of second level amplified differential signals.

8. The method of claim 7, further comprising providing the number of second level amplified signals to a corresponding number of tuners.

9. The method of claim 7, further comprising:

detecting a signal level of each of the number of second level amplified signals;

producing a gain control signal based upon the detected signal level; and

providing the gain control signal as an input to each of the amplifiers of the second amplification module and controlling a gain thereof based upon the provided gain control signal.