Interface circuit system and method for performing power saving operations during a command-related latency

• US 7,581,127 B2
• Filed: 10/20/2006
• Issued: 08/25/2009
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: MetaRAM Incorporated
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US11/584,179
• Publication Number:
  US 20080037353A1
• Time in Patent Office: 1,040 Days
• Field of Search: 713/320, 713/300, 713/323, 713/324, 365/226, 365/227
• US Class Current: 713/320
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2272 Latency related aspects
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at least a portion of the memory circuits. Such power management operation is performed during a latency associated with one or more commands directed to at least a portion of the memory circuits.

Claims

1. A memory apparatus for use with a system, the memory apparatus comprising:

a plurality of memory circuits;

an interface circuit coupled to communicate with the memory circuits, and for communicating with the system, the interface circuit operable to perform a power management operation on at least a portion of the memory circuits during a latency associated with a command directed to at least a portion of the memory circuits.

2. The memory apparatus of claim 1, wherein the power management operation includes:

a power saving operation.

3. The memory apparatus of claim 2, wherein the power saving operation includes:

an entry into a power down mode.

4. The memory apparatus of claim 1, wherein the power management operation includes:

an exit from a power down mode.

5. The memory apparatus of claim 1, wherein:

the interface circuit is further operable to change the latency.

6. The memory apparatus of claim 1, wherein the latency includes at least one of:

a row address to column address latency (tRCD);

a row precharge latency (tRP);

an active to precharge latency (tRAS);

a row cycle time (tRC);

a refresh latency (tRFC); and

a column address strobe (CAS) latency.

7. The memory apparatus of claim 1, wherein the latency includes at least one of:

a write latency; and

a read latency.

8. The memory apparatus of claim 1, wherein:

at least one of the plurality of memory circuits has a first latency; and

the interface circuit is further operable to simulate at least one virtual memory circuit having a second latency that is different than the first latency.

9. The memory apparatus of claim 8 wherein:

the second latency is simulated to accommodate the power management operation.

10. The memory apparatus of claim 1 further comprising:

a dual in-line memory module (DIMM); and

the interface circuit is disposed on the DIMM.

11. The memory apparatus of claim 1, wherein the interface circuit comprises at least one of:

a buffer;

a register; and

an advanced memory buffer (AMB).

12. The memory apparatus of claim 1, wherein the command comprises:

a control signal.

13. The memory apparatus of claim 12, wherein the control signal comprises at least one of:

an address signal; and

a data signal.

14. The memory apparatus of claim 12, wherein the control signal comprises:

a signal in a sequence of control signals.

15. The memory apparatus of claim 12, wherein the control signal comprises:

an encoded signal.

16. The memory apparatus of claim 1, wherein:

the command is associated with an operation.

17. The memory apparatus of claim 16, wherein the operation comprises at least one of:

an activate operation;

a precharge operation;

a write operation;

a read operation;

a mode register write operation;

a mode register read operation; and

a refresh operation.

18. The memory apparatus of claim 1, wherein the command comprises:

an encoded command.

19. The memory apparatus of claim 18, wherein:

the encoded command is associated with an operation.

20. The memory apparatus of claim 1, wherein the command comprises at least one of:

an activate operation;

a precharge operation;

a write operation;

a read operation;

a mode register write operation;

a mode register read operation; and

a refresh operation.

21. The memory apparatus of claim 1, wherein the command comprises:

a signal associated with at least one of,

an activate operation,

a precharge operation,

a write operation,

a read operation,

a mode register write operation,

a mode register read operation, and

a refresh operation.

22. A method of operating a physical memory apparatus, the physical memory apparatus including a plurality of memory circuits and an interface circuit coupled to the plurality of physical memory circuits, the interface circuit further being coupled to a system which issues a command directed to at least a portion of the memory apparatus, the method comprising:

receiving the command; and

during a latency associated with the command, performing a power management operation on at least a portion of the physical memory circuits.

23. The method of claim 22, wherein the command comprises at least one of:

an activate operation;

a precharge operation;

a write operation;

a read operation;

a mode register write operation;

a mode register read operation; and

a refresh operation.

24. The method of claim 23, further comprising:

providing to the system a simulation of a memory apparatus having a simulated latency, wherein the simulated latency differs from a corresponding physical latency of the physical memory circuits;

wherein the difference between the simulated latency and the physical latency provides time for performing the power management operation.

25. A memory apparatus for use with a system which issues a command having a latency determined by a first latency of the memory apparatus, the memory apparatus comprising:

a plurality of physical memory circuits having a second latency; and

an interface circuit coupled to the plurality of physical memory circuits and couplable to the system, for simulating a memory having a the first latency which is different than the second latency, and for informing the system of the first latency, and for performing a power management operation on at least a portion of the physical memory circuits during the first latency.

26. The memory apparatus of claim 25 wherein:

the second latency is shorter than the first latency.