Semiconductor chip having gettering layer, and method for manufacturing the same

• US 7,582,950 B2
• Filed: 07/27/2005
• Issued: 09/01/2009
• Est. Priority Date: 07/28/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Higashide, Yoshiko, Matsukawa, Kazuhito, Koga, Tsuyoshi, Shibata, Jun, Tobimatsu, Hiroshi, Nishida, Akio
• Primary Examiner(s): Ghyka; Alexander G
• Assistant Examiner(s): Roman; Angel
• Application Number:
  US11/190,011
• Publication Number:
  US 20060022321A1
• Time in Patent Office: 1,497 Days
• Field of Search: 257/678, 257/618, 257/620, 257/622, 257/E29.022
• US Class Current: 257/622
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Claims

1. A semiconductor device comprising:

a semiconductor chip which includes an element layer formed on a front face of the semiconductor chip and a gettering layer on a back face of the semiconductor chip;

a package substrate which faces the back face; and

a resin covering the semiconductor chip and the package substrate,

wherein a thickness of said semiconductor chip is 100 μ

m or less,

wherein said gettering layer is a damaged layer,

wherein the damaged layer includes a plurality of grooves,

wherein a depth of each of said grooves is 2 to 3 μ

m, and

wherein in plan view to said semiconductor chip, each of said grooves is a linear groove.

2. A semiconductor device comprising:

a semiconductor chip which includes an element layer formed on a front face of the semiconductor chip and a gettering layer on a back face of the semiconductor chip;

a substrate which faces the back face;

a wire; and

a resin covering the semiconductor chip, the wire and the package substrate,

wherein a thickness of said semiconductor chip is 100 μ

m or less,

wherein said gettering layer is a damaged layer,

wherein the damaged layer includes a plurality of grooves,

wherein a depth of each of said grooves is 2 to 3 μ

m, and

wherein in plan view to said semiconductor chip, each of said grooves is a linear groove, and

wherein the wire electrically connects between the substrate and the semiconductor chip.