Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array

• US 7,584,438 B2
• Filed: 06/01/2007
• Issued: 09/01/2009
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Moroz, Victor, Pramanik, Dipankar
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Tat; Binh C
• Application Number:
  US11/757,335
• Publication Number:
  US 20080301599A1
• Time in Patent Office: 823 Days
• Field of Search: 716 4- 6
• US Class Current: 716/136
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.

Claims

1. An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout, comprising the steps of:

selecting a diffusion area within the layout for analysis;

identifying Si/STI edges on the selected area;

identifying channel areas and their associated gate/Si edges;

determining threshold voltage variations in each identified channel area, including the steps of

calculating, by a computer, threshold voltage variations due to effects in a longitudinal direction;

calculating, by the computer, threshold voltage variations due to effects in a transverse direction; and

combining, by the computer, the longitudinal and transverse variations to provide an overall variation,

wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function of the form

λ

_i(r)=1/((x_i/α

)<sup>β

i</sup>+ε

_i),

wherein, α

_i, β

_i and ε

_i, are process and material-related factors, and r is a distance in either the X or Y direction.

2. An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout, comprising the steps of:

selecting a diffusion area within the layout for analysis;

identifying Si/STI edges on the selected area;

identifying channel areas and their associated gate/Si edges;

determining threshold voltage variations in each identified channel area, including the steps of

calculating, by a computer, threshold voltage variations due to effects in a longitudinal direction;

calculating, by the computer, threshold voltage variations due to effects in a transverse direction; and

combining, by the computer, the longitudinal and transverse variations to provide an overall variation,

wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function,

wherein threshold voltage variations due to effects in a longitudinal direction are calculated according to a decay function,

λ

_i(x)=1/((x_i/α

)<sup>β

i</sup>+ε

_i),

where α

_i, β

_i and ε

_i, are process and material-related factors; and

threshold voltage variations due to effects in a transverse direction are calculated according to the complementary error function, erfc.

3. A system for automated estimation of layout-induced variations in threshold voltage in an integrated circuit layout, comprising:

a digital computer, including a processor, display means and data storage means storing a computer program configured to perform the steps of

selecting a diffusion area within the layout for analysis;

identifying Si/STI edges on the selected area;

identifying channel areas and their associated gate/Si edges;

determining threshold voltage variations in each identified channel area, including the steps of

calculating threshold voltage variations due to effects in a longitudinal direction;

calculating threshold voltage variations due to effects in a transverse direction; and

combining the longitudinal and transverse variations to provide an overall variation,

wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function of the form

λ

_i(r)=1/((x_i/α

)<sup>β

i</sup>+ε

_i),

where α

_i, β

_i and ε

_i, are process and material-related factors.

4. A system for automated estimation of layout-induced variations in threshold voltage in an integrated circuit layout, comprising:

a digital computer, including a processor, display means and data storage means storing a computer program configured to perform the steps of

selecting a diffusion area within the layout for analysis;

identifying Si/STI edges on the selected area;

identifying channel areas and their associated gate/Si edges;

determining threshold voltage variations in each identified channel area, including the steps of

calculating threshold voltage variations due to effects in a longitudinal direction;

calculating threshold voltage variations due to effects in a transverse direction; and

combining the longitudinal and transverse variations to provide an overall variation,

wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function,

wherein threshold voltage variations due to effects in a longitudinal direction are calculated according to a decay function,

λ

_i(r)=1/((x_i/α

)<sup>β

i</sup>+ε

_i),

where α

_i, β

_i and ε

_i, are process and material-related factors; and

threshold voltage variations due to effects in a transverse direction are calculated according to the complementary error function, erfc.

5. Data storage means for use with a digital computer having a processor, the data storage means having stored thereon a computer program configured to perform the steps of

selecting a diffusion area within the layout for analysis;

identifying Si/STI edges on the selected area;

identifying channel areas and their associated gate/Si edges;

determining threshold voltage variations in each identified channel area, including the steps of

calculating threshold voltage variations due to effects in a longitudinal direction;

calculating threshold voltage variations due to effects in a transverse direction; and

combining the longitudinal and transverse variations to provide an overall variation,

wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function of the form

λ

_i(r)=1/((x_i/α

)<sup>β

i</sup>+ε

_i),

where α

_i, β

_i and ε

_i, are process and material-related factors, and r is a distance in either the X or Y direction.

6. Data storage means for use with a digital computer having a processor, the data storage means having stored thereon a computer program configured to perform the steps of

selecting a diffusion area within the layout for analysis;

identifying Si/STI edges on the selected area;

identifying channel areas and their associated gate/Si edges;

determining threshold voltage variations in each identified channel area, including the steps of

calculating threshold voltage variations due to effects in a longitudinal direction;

calculating threshold voltage variations due to effects in a transverse direction; and

combining the longitudinal and transverse variations to provide an overall variation,

wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function,

wherein threshold voltage variations due to effects in a longitudinal direction are calculated according to a decay function,

λ

_i(x)=1/((xi/α

)<sup>β

i</sup>+ε

_i),

where α

_i, β

_i and ε

_i, are process and material-related factors; and

threshold voltage variations due to effects in a transverse direction are calculated according to the complementary error function, erfc.