System and method of mapping memory blocks in a configurable integrated circuit

• US 7,587,697 B1
• Filed: 12/12/2006
• Issued: 09/08/2009
• Est. Priority Date: 12/12/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Pugh, Daniel J., Teig, Steven
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US11/609,883
• Time in Patent Office: 1,001 Days
• Field of Search: 716/16, 716/18
• US Class Current: 716/138
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.

Claims

1. A method of implementing a user design on a configurable integrated circuit (IC), said method comprising:

a) receiving said user design wherein said user design comprises a plurality of user design memory blocks;

b) mapping a first user design memory block of said plurality of user design memory blocks to a first set of addresses of a physical memory;

c) mapping a second user design memory block of said plurality of user design memory blocks to a second set of addresses of said physical memory, wherein said first set of addresses does not overlap with said second set of addresses;

d) mapping a first user design memory port to a first subcycle and a memory port of said physical memory; and

e) mapping a second user design memory port to a second subcycle and said memory port of said physical memory.

2. The method of claim 1, wherein said first user design memory port is for accessing said first user design memory block.

3. The method of claim 2, wherein said second user design memory port is for accessing said second user design memory block.

4. The method of claim 1, further comprising:

a) mapping a third user design memory block of said plurality of user design memory blocks to a third set of addresses of said physical memory; and

b) mapping a third user design memory port to a third subcycle and said memory port of said physical memory.

5. The method of claim 1, wherein said user design is expressed in RTL code.

6. The method of claim 1, further comprising determining that said user design allows for N potential operations, during a user design clock cycle, before an access of said first user design memory block, wherein N is a number of at least one.

7. The method of claim 6, wherein said first subcycle has at least N subcycles before it in each user design clock cycle.

8. The method of claim 1, further comprising determining that said user design allows for N potential operations, during a user design clock cycle, after an access of said first user design memory block, wherein N is a number of at least one.

9. The method of claim 8, wherein said first subcycle has at least N subcycles after it in each user design clock cycle.

10. The method of claim 8, further comprising determining that said user design allows for M potential operations, during a user design clock cycle, before an access of said first user design memory block, wherein M is a number of at least one.