Semiconductor device with STI and its manufacture

• US 7,589,391 B2
• Filed: 05/15/2006
• Issued: 09/15/2009
• Est. Priority Date: 03/18/2002
• Status: Expired due to Fees

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Inventors: Iriyama, Yasunori, Ohta, Hiroyuki
• Primary Examiner(s): Ha; Nathan W
• Application Number:
  US11/433,671
• Publication Number:
  US 20060202301A1
• Time in Patent Office: 1,219 Days
• Field of Search: 257506-510, 257/369, 257/E21.545
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from the surface of the silicon substrate; a first liner insulating film formed on the surface of the trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; a second liner insulating film formed on the first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and an isolation region burying the trench defined by the second liner insulating film.

Claims

1. A semiconductor device comprising:

a silicon substrate;

an isolation trench formed in said silicon substrate for isolating n-type and p-type active regions in said silicon substrate, said isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from a surface of said silicon substrate, and said active regions having flat upper surfaces;

a liner insulating film formed on a surface of said isolation trench surrounding said n-type and p-type active regions and a silicon nitride film having a thickness of 2 to 8 nm;

an isolation region burying said trench defined by said liner insulating film;

an n-channel MOS transistor formed in said p-type active region with a first gate electrode formed over said p-type active region; and

a p-channel MOS transistor formed in said n-type active region with a second gate electrode formed over said n-type active region;

wherein said silicon nitride film extends from side walls of said trench to partially overlay said flat upper surfaces of the active regions; and

wherein each of said gate electrodes is formed over the flat upper surface of the active region, said liner insulating film on the flat upper surface of the active region, and said isolation region so as to traverse the active region.

2. A semiconductor device according to claim 1, wherein said isolation region includes a portion extending on said liner insulating layer above the upper surface of said silicon substrate.

3. A semiconductor device according to claim 2, wherein said liner insulating film includes a portion extending on side walls of said extending portion of said isolation region.

4. A semiconductor device according to claim 1, wherein said first gate electrode extends on the isolation region to be continuous to said second gate electrode.

5. A semiconductor device comprising:

a silicon substrate;

an isolation trench formed in said silicon substrate for isolating active regions in said silicon substrate, said isolation trench having generally a trapezoidal cross sectional shape having a width gradually narrowing with a depth from a surface of said silicon substrate and having a gradually broadening upper portion, said isolation trench defining the active regions, said active regions having rounded shoulders, and flat upper surfaces, and forming n-type and p-type wells;

a liner insulating film formed in direct contact with a surface of said trench and made of a silicon nitride film having a thickness of 2 to 8 nm;

an isolation region burying said trench defined by said liner insulating film;

a gate electrode formed over said active region, said liner insulating film on the flat upper surface of the active region, and said isolation region, so as to traverse the active region.

6. A semiconductor device according to claim 5, wherein an upper end of said liner insulating film is retracted by less than about 10 nm from the surface of said silicon substrate.

7. A semiconductor device according to claim 5, wherein said liner insulating film has a tensile stress of 1 GPa or larger.

8. A semiconductor device according to claim 5, wherein said gate electrode traverses the n-type and p-type wells.