Method for the generation of variable pitch nested lines and/or contact holes using fixed size pixels for direct-write lithographic systems

• US 7,589,819 B2
• Filed: 06/15/2006
• Issued: 09/15/2009
• Est. Priority Date: 05/16/2003
• Status: Active Grant

• Current Assignee: ASML Holding NV
• Original Assignee: ASML Holding NV
• Inventors: Baba-Ali, Nabila
• Primary Examiner(s): Mathews; Alan A
• Application Number:
  US11/453,039
• Publication Number:
  US 20060236295A1
• Time in Patent Office: 1,188 Days
• Field of Search: 355/53, 355/67, 355/71, 355/77, 430/22, 430/30, 716 19- 21
• US Class Current: 355/53
• CPC Class Codes: G03F 7/70283 Mask effects on the imaging process
• CPC Class Codes: G03F 7/70291 Addressable masks, e.g. spatial light modulators [SLMs], digital micro-mirror devices [DMDs] or liquid crystal display [LCD] patterning devices
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors

Abstract

Provided is a method and system for developing a lithographic mask layout. The lithographic mask layout is adapted for configuring an array of micro-mirrors in a maskless lithography system. The method includes generating an ideal mask layout representative of image characteristics associated with a desired image. Next, an equivalent mask is produced in accordance with an average intensity of the ideal mask layout.

Claims

1. An apparatus comprising:

a memory; and

one or more processors coupled to the memory and configured to,

generate an ideal mask layout representative of image characteristics associated with a desired image, and

generate an equivalent array-of-mirrors layout in accordance with an average intensity of the ideal mask layout.

2. The apparatus of claim 1, wherein the ideal mask layout representative of the image characteristics comprises a binary mask layout representative of the image characteristics.

3. The apparatus of claim 2, wherein the characteristics include at least one of pitch and image position.

4. The apparatus of claim 1, wherein:

each mirror in the array of mirrors has a predetermined mirror width; and

the image characteristics are independent of the predetermined mirror width.

5. The apparatus of claim 1, wherein the ideal mask layout has a mask transmission that can vary continuously.

6. The apparatus of claim 5, wherein the the one or more processors being configured to generate the equivalent array-of-mirrors layout includes the one or more processors being configured to (i) determine a pitch of the desired image and (ii) form a mirror-based masked pattern, the mirror-based masked pattern being a function of the desired image pitch and the mirror width.

7. The apparatus of claim 1, wherein the equivalent array-of-mirrors layout is representative of the desired image in a wafer plane.

8. The apparatus of claim 1, wherein:

the equivalent array-of-mirrors layout corresponds to a number of pattern pixels; and

each of the pixels includes a width and an intensity value, each intensity value being determined by averaging intensity values of a corresponding portion of the ideal mask layout, each pixel intensity value being associated with a corresponding grey-tone level.

9. The apparatus of claim 1, further comprising a simulation tool configured to produce one or more images in accordance with the equivalent array-of-mirrors layout.

10. The apparatus of claim 9, wherein the one or more processors are further configured to determine performance metrics of at least one of the one or more images.

11. The apparatus of claim 10, wherein the performance metrics include at least one from the group including critical dimension, normalized image log slope, and image position.

12. The apparatus of claim 11, wherein the one or more processors are further configured to optimize the performance metrics when the performance metrics do not satisfy predetermined quality requirements.

13. The apparatus of claim 12, wherein the one or more processors being configured to optimize the performance metrics includes at least one from the group including the one or more processors being configured to (a) shift the one or more simulated images in the wafer plane, (b) perturb the grey-tone level of selected ones of the pixels, (c) convert the grey-tone levels to tilt angles when the mirrors are tiltable, and (d) perturb tilt angles.