Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth

• US 7,598,788 B2
• Filed: 12/28/2005
• Issued: 10/06/2009
• Est. Priority Date: 09/06/2005
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Cao, Jun
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US11/320,401
• Publication Number:
  US 20070052467A1
• Time in Patent Office: 1,378 Days
• Field of Search: 327/266, 327/274, 327/280, 327/287
• US Class Current: 327/266
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00208 using differential stages
• CPC Class Codes: H03K 3/356034 the input circuit having a differential configuration
• CPC Class Codes: H03K 5/07 by the use of resonant circuits
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/145 by the use of resonant circuits

Abstract

Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.

Claims

1. A current-controlled CMOS (C3MOS) wideband variable delay cell circuit, the circuit comprising:

a first differential transistor having a first source, a first gate, and a first drain;

a second differential transistor having a second source that is directly coupled to the first source of the first differential transistor, a second gate, and a second drain;

a first variable current source transistor such that a drain of the first variable current source transistor is directly coupled to the directly coupled first source and second source and a source of the first variable current source transistor is grounded;

a first lumped input impedance component that is directly coupled between a first differential input of the C3MOS wideband variable delay cell circuit and the first gate of the first differential transistor;

a second lumped input impedance component that is directly coupled between a second differential input of the C3MOS wideband variable delay cell circuit and the second gate of the second differential transistor;

a first output impedance, having a first output resistor and a first shunt peaking inductor connected in series, that is directly coupled between the first drain of the first differential transistor and a supply voltage;

a second output impedance, having a second output resistor and a second shunt peaking inductor connected in series, that is directly coupled between the second drain of the second differential transistor and the supply voltage;

a third differential transistor having a third source, a third gate, and a third drain;

a fourth differential transistor having a fourth source that is directly coupled to the third source of the third differential transistor, a fourth gate, and a fourth drain;

a second variable current source transistor such that a drain of the second variable current source transistor is directly coupled to the directly coupled third source and fourth source and a source of the second variable current source transistor is grounded; and

a control module that;

adjusts a delay of the C3MOS wideband variable delay cell circuit by adjusting a first DC bias voltage provided to a gate of the first variable current source transistor to set a first DC bias current in the first variable current source transistor and by adjusting a second DC bias voltage provided to a gate of the second variable current source transistor to set a second DC bias current in the second variable current source transistor; and

keeps a sum of the first DC bias current in the first variable current source transistor and the second DC bias current in the second variable current source transistor constant; and

wherein;

the first lumped input impedance component and the second lumped input impedance component operate to perform bandwidth expansion of the wideband differential transistor pair;

the first drain of the first differential transistor, the third drain of the third differential transistor, and the fourth gate of the fourth differential transistor are directly coupled at a first node that is a first differential output of the C3MOS wideband variable delay cell circuit; and

the second drain of the second differential transistor, the fourth drain of the fourth differential transistor, and the third gate of the third differential transistor are directly coupled at a second node that is a second differential output of the C3MOS wideband variable delay cell circuit.

2. The circuit of claim 1, further comprising:

a first capacitor that is coupled between the first drain of the first differential transistor and the second gate of the second differential transistor; and

a second capacitor that is coupled between the second drain of the second differential transistor and the first gate of the first differential transistor.

3. The circuit of claim 1, wherein:

the first lumped input impedance component comprises a first series inductor; and

the second lumped input impedance component comprises a second series inductor.

4. The circuit of claim 1, wherein:

the first output resistor of the first output impedance is coupled between the first drain of the first differential transistor and the first shunt peaking inductor of the first output impedance; and

the first shunt peaking inductor of the first output impedance is coupled between the first output resistor of the first output impedance and the supply voltage.

5. The circuit of claim 1, wherein:

the first differential transistor, the second differential transistor, the third differential transistor, the fourth differential transistor, the first variable current source transistor, and the second variable current source transistor comprise NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.

6. The circuit of claim 1, wherein:

the first differential transistor, the second differential transistor, the third differential transistor, the fourth differential transistor, the first variable current source transistor, and the second variable current source transistor comprise PMOS (Positive-Channel Metal-Oxide Semiconductor) transistors.

7. The circuit of claim 1, wherein:

the control module keeps a DC level output of the first differential output of the C3MOS wideband variable delay cell circuit and the second differential output of the C3MOS wideband variable delay cell circuit constant by keeping the sum of the first DC bias current in the first variable current source transistor and the second DC bias current in the second variable current source transistor being constant.

8. The circuit of claim 1, wherein:

the delay of the C3MOS wideband variable delay cell circuit is a function of a ratio of the first DC bias current in the first variable current source transistor divided by the sum of the first DC bias current in the first variable current source transistor and the second DC bias current in the second variable current source transistor.

9. The circuit of claim 1, wherein:

the C3MOS wideband variable delay cell circuit is one delay cell of a plurality of delay cells implemented within an n-tap finite impulse response (FIR) filter.

10. A current-controlled CMOS (C3MOS) wideband variable delay cell circuit, the circuit comprising:

a wideband differential transistor pair having a first differential input, a second differential input, a first differential output, and a second differential output;

a first variable current source transistor, such that a drain of the first variable current source transistor is directly coupled to directly coupled sources of the wideband differential transistor pair and a source of the first variable current source transistor is grounded, that is operable to provide first DC bias current to the wideband differential transistor pair;

a cross-coupled differential transistor pair having a third differential input, a fourth differential input, a third differential output, and a fourth differential output;

a second variable current source transistor, such that a drain of the second variable current source transistor is directly coupled to directly coupled sources of the cross-coupled differential transistor pair and a source of the second variable current source transistor is grounded, that is operable to provide second DC bias current to the cross-coupled differential transistor pair;

a first lumped input impedance component that directly couples a first differential input signal to the first differential input of the wideband differential transistor pair;

a second lumped input impedance component that directly couples a second differential input signal to the second differential input of the wideband differential transistor pair;

a first output impedance that directly couples the first differential output of the wideband differential transistor pair to a power supply voltage;

a second output impedance that directly couples the second differential output of the wideband differential transistor pair to the power supply voltage; and

a control module that;

adjusts a delay of the C3MOS wideband variable delay cell circuit by adjusting a first DC bias voltage provided to a gate of the first variable current source transistor to set the first DC bias current in the first variable current source transistor and by adjusting a second DC bias voltage provided to a gate of the second variable current source transistor to set the second DC bias current in the second variable current source transistor; and

keeps a sum of the first DC bias current in the first variable current source transistor and the second DC bias current in the second variable current source transistor constant; and

wherein;

the first lumped input impedance component and the second lumped input impedance component operate to perform bandwidth expansion of the wideband differential transistor pair;

the second differential output of the wideband differential transistor pair, the third differential input of the cross-coupled differential transistor pair, and the third differential output of the cross-coupled differential transistor pair are directly coupled at a first node that is a first differential output of the C3MOS wideband variable delay cell circuit; and

the first differential output of the wideband differential transistor pair, the fourth differential input of the cross-coupled differential transistor pair, and the fourth differential output of the cross-coupled differential transistor pair are directly coupled at a second node that is a second differential output of the C3MOS wideband variable delay cell circuit.

11. The circuit of claim 10, wherein:

the delay of the C3MOS wideband variable delay cell circuit is a function of a ratio of the first DC bias current in the first variable current source transistor divided by the sum of the first DC bias current in the first variable current source transistor and the second DC bias current in the second variable current source transistor.

12. The circuit of claim 10, wherein:

the wideband differential transistor pair comprises;

a first differential transistor having a first source, a first gate that comprises the first differential input of the wideband differential transistor pair, and a first drain that comprises the second differential output of the wideband differential transistor pair;

a second differential transistor having a second source, a second gate that comprises the second differential input of the wideband differential transistor pair, and a second drain that comprises the first differential output of the wideband differential transistor pair; and

wherein the drain of the first variable current source transistor is directly coupled to the first source of the first differential transistor and to the second source of the second differential transistor;

the cross-coupled differential transistor pair comprises;

a third differential transistor having a third source, a third gate, and a third drain;

a fourth differential transistor having a fourth source, a fourth gate, and a fourth drain; and

wherein the drain of the second variable current source transistor is directly coupled to the third source of the third differential transistor and to the fourth source of the fourth differential transistor;

the first drain of the first differential transistor, the third drain of the third differential transistor, and the fourth gate of the fourth differential transistor are directly coupled; and

the second drain of the second differential transistor, the fourth drain of the third differential transistor, and the third gate of the third differential transistor are directly coupled.

13. The circuit of claim 10, wherein:

a first capacitor that is coupled between the first differential input of the wideband differential transistor pair and the first differential output of the wideband differential transistor pair; and

a second capacitor that is coupled between the second differential input of the wideband differential transistor pair and the second differential output of the wideband differential transistor pair.

14. The circuit of claim 10, wherein:

the first lumped input impedance component comprises a first series inductor; and

the second lumped input impedance component comprises a second series inductor.

15. The circuit of claim 10, wherein:

the first output impedance comprises a first output resistor and a first shunt peaking inductor connected in series; and

the second output impedance comprises a second output resistor and a second shunt peaking inductor connected in series.

16. A current-controlled CMOS (C3MOS) wideband variable delay cell circuit, the circuit comprising:

a first differential transistor having a first source, a first gate, and a first drain;

a second differential transistor having a second source that is directly coupled to the first source of the first differential transistor, a second gate, and a second drain;

a first variable current source transistor such that a drain of the first variable current source transistor is directly coupled to the directly coupled first source and second source and a source of the first variable current source transistor is grounded;

a first series inductor that is directly coupled between a first differential input of the C3MOS wideband variable delay cell circuit and the first gate of the first differential transistor;

a second series inductor that is directly coupled between a second differential input of the C3MOS wideband variable delay cell circuit and the second gate of the second differential transistor;

a first output impedance, having a first output resistor and a first shunt peaking inductor connected in series, such that the first output resistor is directly coupled between the drain of the first differential transistor and the first shunt peaking inductor, and the first shunt peaking inductor is directly coupled between the first output resistor and a supply voltage;

a second output impedance, having a second output resistor and a second shunt peaking inductor connected in series, such that the second output resistor is directly coupled between the drain of the second differential transistor and the second shunt peaking inductor, and the second shunt peaking inductor is directly coupled between the second output resistor and the supply voltage;

a first capacitor that is directly coupled between the drain of the first differential transistor and the gate of the second differential transistor;

a second capacitor that is directly coupled between the drain of the second differential transistor and the gate of the first differential transistor;

a third differential transistor having a third source, a third gate, and a third drain;

a fourth differential transistor having a fourth source that is directly coupled to the third source of the third differential transistor, a fourth gate, and a fourth drain;

a second variable current source transistor such that a drain of the second variable current source transistor is directly coupled between the directly coupled third source and fourth source and a source of the second variable current source transistor is grounded; and

a control module that;

adjusts a delay of the C3MOS wideband variable delay cell circuit by adjusting a first DC bias voltage provided to a gate of the first variable current source transistor to set a first DC bias current in the first variable current source transistor and by adjusting a second DC bias voltage provided to a gate of the second variable current source transistor to set a second DC bias current in the second variable current source transistor; and

keeps a sum of the first DC bias current in the first variable current source transistor and the second DC bias current in the second variable current source transistor constant; and

wherein;

the first drain of the first differential transistor, the third drain of the third differential transistor, and the fourth gate of the fourth differential transistor are directly coupled at a first node that is a first differential output of the C3MOS wideband variable delay cell circuit; and

the second drain of the second differential transistor, the fourth drain of the fourth differential transistor, and the third gate of the third differential transistor are directly coupled at a second node that is a second differential output of the C3MOS wideband variable delay cell circuit.

17. The circuit of claim 16, wherein:

the control module keeps a DC level output of the first differential output of the C3MOS wideband variable delay cell circuit and the second differential output of the C3MOS wideband variable delay cell circuit constant by keeping the sum of the first DC bias current in the first variable current source transistor and the second DC bias current in the second variable current source transistor being constant.

18. The circuit of claim 16, wherein:

the delay of the C3MOS wideband variable delay cell circuit is a function of a ratio of the first DC bias current in the first variable current source transistor divided by the sum of the first DC bias current in the first variable current source transistor and the second DC bias current in the second variable current source transistor.

19. The circuit of claim 16, wherein:

the C3MOS wideband variable delay cell circuit is one delay cell of a plurality of delay cells implemented within an n-tap finite impulse response (FIR) filter.

20. The circuit of claim 16, wherein:

the first differential transistor, the second differential transistor, the third differential transistor, the fourth differential transistor, the first variable current source transistor, and the second variable current source transistor comprise NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors or PMOS (Positive-Channel Metal-Oxide Semiconductor) transistors.