Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading

• US 7,598,811 B2
• Filed: 12/28/2005
• Issued: 10/06/2009
• Est. Priority Date: 07/29/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.), Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Cao, Jun
• Primary Examiner(s): Nguyen; Khanh V
• Application Number:
  US11/320,398
• Publication Number:
  US 20070025435A1
• Time in Patent Office: 1,378 Days
• Field of Search: 330/253, 330/254, 330/304, 330/259, 330/260
• US Class Current: 330/304
• CPC Class Codes: H03F 2200/405 the output amplifying stage of an amplifier comprising more than three power stages
• CPC Class Codes: H03F 2203/45134 the whole differential amplifier together with other coupled stages being fully differential realised
• CPC Class Codes: H03F 2203/45332 the AAC comprising one or more capacitors as feedback circuit elements
• CPC Class Codes: H03F 2203/45466 the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 2203/45504 the CSC comprising more than one switch
• CPC Class Codes: H03F 2203/45554 the IC comprising one or more coils
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45197 Pl types H03F3/45224, H03F3/45251 take precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated

Abstract

Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading. A novel approach is presented by which adjustable amplification and equalizer may be achieved using a C3MOS wideband data stage. This may be referred to as a C3MOS wideband data amplifier/equalizer circuit. This employs a wideband differential transistor pair that is fed using two separate transistor current sources. A switchable RC network is communicatively coupled between the sources of the individual transistors of the wideband differential transistor pair. There are a variety of means by which the switchable RC network may be implemented, including using a plurality of components (e.g., capacitors and resistors connected in parallel). In such an embodiment, each component may have an individual switch to govern its connectivity in the switchable RC network thereby allowing a broad range of amplification and equalization to be performed.

Claims

1. A current-controlled CMOS (C3MOS) wideband data amplifier/equalizer circuit having adjustable gain and frequency response, the circuit comprising:

a first differential transistor comprising a source, gate, and drain;

a second differential transistor comprising a source, gate, and drain;

a first current source that is coupled to the source of the first differential transistor;

a second current source that is coupled to the source of the second differential transistor;

a first output impedance, comprising a first output resistor and a first shunt peaking inductor connected in series, that is coupled between the drain of the first differential transistor and a supply voltage;

a second output impedance, comprising a second output resistor and a second shunt peaking inductor connected in series, that is coupled between the drain of the second differential transistor and the supply voltage;

a first input impedance that is coupled between a first differential input of the C3MOS wideband data amplifier circuit and the gate of the first differential transistor; and

a second input impedance that is coupled between a second differential input of the C3MOS wideband data amplifier circuit and the gate of the second differential transistor;

a first capacitor that is coupled between the drain of the first differential transistor and the gate of the second differential transistor;

a second capacitor that is coupled between the drain of the second differential transistor and the gate of the first differential transistor; and

a switchable RC network, comprising a resistor and a capacitor connected in parallel, that is coupled between the source of the first differential transistor and the source of the second differential transistor.

2. The circuit of claim 1, wherein:

the first input impedance comprises a first series inductor; and

the second input impedance comprises a second series inductor.

3. The circuit of claim 1, wherein:

the switchable RC network comprises a plurality of resistors, that includes the resistor, connected in parallel; and

the switchable RC network comprises a plurality of switches that corresponds to the plurality of resistors such that the plurality of switches allows selection of an integer number of resistors that corresponds to the resistor of the plurality of resistors and all resistors of the plurality of resistors.

4. The circuit of claim 1, wherein:

the resistor of the switchable RC network is a variable resistor; and

the capacitor of the switchable RC network is a variable capacitor.

5. The circuit of claim 1, wherein:

the resistor of the switchable RC network is a variable resistor that is implemented as either a PMOS (Positive-Channel Metal-Oxide Semiconductor) or an NMOS (Negative-Channel Metal-Oxide Semiconductor) transistor comprising a source, gate, and drain; and

a gate voltage of the PMOS or the NMOS transistor controls a conductivity of the PMOS or the NMOS transistor thereby determining a resistance of the PMOS or the NMOS transistor.

6. The circuit of claim 1, wherein:

a value of the resistor of the switchable RC network is operable to control a boost between a low frequency gain and a high frequency gain of the C3MOS wideband data amplifier/equalizer circuit; and

a value of the capacitor of the switchable RC network is operable to control a peaking frequency of the C3MOS wideband data amplifier/equalizer circuit.

7. The circuit of claim 1, wherein:

the switchable RC network is operable to select an impedance from a plurality of impedances that includes zero impedance between the source of the first differential transistor and the source of the second differential transistor.

8. The circuit of claim 1, wherein:

the switchable RC network is operable to short the source of the first differential transistor to the source of the second differential transistor.

9. The circuit of claim 1, wherein:

the first output resistor of the first output impedance is coupled between the drain of the first differential transistor and the first shunt peaking inductor of the first output impedance; and

the first shunt peaking inductor of the first output impedance is coupled between the first output resistor of the first output impedance and the supply voltage.

10. The circuit of claim 1, wherein:

the first current source is a first current source transistor;

the second current source is a second current source transistor; and

the first differential transistor, the second differential transistor, the first current source transistor, and the second current source transistor comprise NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.

11. The circuit of claim 1, wherein:

the first current source is a first current source transistor;

the second current source is a second current source transistor; and

the first differential transistor, the second differential transistor, the first current source transistor, and the second current source transistor comprise PMOS (Positive-Channel Metal-Oxide Semiconductor) transistors.

12. The circuit of claim 1, wherein:

the C3MOS wideband data amplifier/equalizer circuit is one stage of a cascaded plurality of stages in an upstream path or a downstream path in an integrated circuit; and

the integrated circuit is implemented within a receiver functional block of a communication transceiver.

13. A current-controlled CMOS (C3MOS) wideband data amplifier/equalizer circuit having adjustable gain and frequency response, the circuit comprising:

a first differential transistor comprising a source, gate, and drain;

a second differential transistor comprising a source, gate, and drain;

a first current source that is coupled to the source of the first differential transistor;

a second current source that is coupled to the source of the second differential transistor;

a first output impedance, comprising a first output resistor and a first shunt peaking inductor connected in series, that is coupled between the drain of the first differential transistor and a supply voltage;

a second output impedance, comprising a second output resistor and a second shunt peaking inductor connected in series, that is coupled between the drain of the second differential transistor and the supply voltage; and

a switchable RC network, comprising a resistor and a capacitor connected in parallel, that is coupled between the source of the first differential transistor and the source of the second differential transistor; and

wherein;

the switchable RC network is operable to select an impedance from a plurality of impedances between the source of the first differential transistor and the source of the second differential transistor.

14. The circuit of claim 13, further comprising:

a first series inductor that is coupled between a first differential input of the C3MOS wideband data amplifier circuit and the gate of the first differential transistor; and

a second series inductor that is coupled between a second differential input of the C3MOS wideband data amplifier circuit and the gate of the second differential transistor;

a first capacitor that is coupled between the drain of the first differential transistor and the gate of the second differential transistor; and

a second capacitor that is coupled between the drain of the second differential transistor and the gate of the first differential transistor.

15. The circuit of claim 13, wherein:

the resistor of the switchable RC network is a variable resistor; and

the capacitor of the switchable RC network is a variable capacitor.

16. The circuit of claim 13, wherein:

a value of the resistor of the switchable RC network is operable to control a boost between a low frequency gain and a high frequency gain of the C3MOS wideband data amplifier/equalizer circuit; and

a value of the capacitor of the switchable RC network is operable to control a peaking frequency of the C3MOS wideband data amplifier/equalizer circuit.

17. The circuit of claim 13, wherein:

the switchable RC network is operable to short the source of the first differential transistor to the source of the second differential transistor.

18. A current-controlled CMOS (C3MOS) wideband data amplifier/equalizer circuit having adjustable gain and frequency response, the circuit comprising:

a first differential transistor comprising a source, gate, and drain;

a second differential transistor comprising a source, gate, and drain;

a first current source that is coupled to the source of the first differential transistor;

a second current source that is coupled to the source of the second differential transistor;

a first output impedance, comprising a first output resistor and a first shunt peaking inductor connected in series, such that the first output resistor is coupled between the drain of the first differential transistor and the first shunt peaking inductor, and the first shunt peaking inductor is coupled between the first output resistor and a supply voltage;

a second output impedance, comprising a second output resistor and a second shunt peaking inductor connected in series, such that the second output resistor is coupled between the drain of the second differential transistor and the second shunt peaking inductor, and the second shunt peaking inductor is coupled between the second output resistor and the supply voltage;

a first series inductor that is coupled between a first differential input of the C3MOS wideband data amplifier circuit and the gate of the first differential transistor; and

a second series inductor that is coupled between a second differential input of the C3MOS wideband data amplifier circuit and the gate of the second differential transistor;

a first capacitor that is coupled between the drain of the first differential transistor and the gate of the second differential transistor;

a second capacitor that is coupled between the drain of the second differential transistor and the gate of the first differential transistor; and

a switchable RC network, comprising a variable resistor and a variable capacitor connected in parallel, that is coupled between the source of the first differential transistor and the source of the second differential transistor.

19. The circuit of claim 18, wherein:

a value of the variable resistor of the switchable RC network is operable to control a boost between a low frequency gain and a high frequency gain of the C3MOS wideband data amplifier/equalizer circuit; and

a value of the variable capacitor of the switchable RC network is operable to control a peaking frequency of the C3MOS wideband data amplifier/equalizer circuit.

20. The circuit of claim 18, wherein:

the C3MOS wideband data amplifier/equalizer circuit is one stage of a cascaded plurality of stages in an upstream path or a downstream path in an integrated circuit; and

the integrated circuit is implemented within a receiver functional block of a communication transceiver.