Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects

• US 7,601,607 B2
• Filed: 05/15/2006
• Issued: 10/13/2009
• Est. Priority Date: 05/15/2006
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Joy, Raymond, Seah, Boon Meng, Pal, Shyam, Liu, Wuping, Hsia, Liang Choo, Zhang, Beichao
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US11/434,318
• Publication Number:
  US 20070264820A1
• Time in Patent Office: 1,247 Days
• Field of Search: 438637-640, 438738-739, 438/717, 438424-437, 438/629, 438/643, 438/692, 438/693, 438/700, 438/706, 438/723, 438/724, 438/743, 438/758, 257/E21.035, 257/233, 257/244, 257/546, 257/549, 257/551, 257/572
• US Class Current: 438/424
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31133 by chemical means
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

Abstract

An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

Claims

1. A method of fabrication of an interconnect opening for a semiconductor device;

comprising the steps of;

forming a lower interconnect and an insulating layer over a semiconductor structure;

forming a first hardmask over said lower interconnect and said insulating layer;

forming a dielectric layer over said first hardmask layer;

forming a second hardmask over said dielectric layer;

in a first etch step, etching a first interconnect opening in said first hardmask, said dielectric layer and said second hardmask layer;

the dielectric layer in said first interconnect opening has sidewalls;

the first hardmask has an first hardmask overhang and the second hardmask has a second hardmask overhang where said first hardmask overhang and said second hardmask overhang extend out past the sidewall of the dielectric layer;

in a second etch step, etching the first and second hardmask overhangs and the dielectric layer form a first overhang-less interconnect opening;

the second etch step essentially removes said first and second hardmask overhangs;

forming an interconnect in said first overhang-less interconnect opening.

2. The method of claim 1 wherein in the first etch step, the etch has an etch selectivity from the dielectric layer to the first and second hardmasks between 1:

1 and 2;

1.

3. The method of claim 1 wherein in the second etch step, the etch has an etch selectivity between the dielectric layer and the first and second hardmasks between about 1:

5 and 1;

100.

4. The method of claim 1 which further in comprises:

the first etch forms a damaged dielectric liner on said sidewalls of the dielectric layer;

said damaged dielectric liner is comprised of a nonstoichiometric oxide;

the second etch removes said damaged dielectric liner.

5. The method of claims 1 wherein said first hardmask and said second hardmask are comprised of oxide doped oxide;

a fluorine doped oxide or low-temperature oxide; and

has a thickness between 500 and 1000 angstroms.

6. The method of claim 1 wherein said dielectric layer is comprised of a low K material or ultra low K material.

7. The method of claim 1 wherein said dielectric layer is comprised of:

carbon doped oxide (SiCOH), carbon containing low K dielectric with a dielectric constant less than 3.0, spin on low-k dielectrics or CVD ultra-low-k dielectrics and has a thickness between 1500 and 3000 angstroms.

8. The method of claim 1 wherein said first hardmask and said second hardmask is comprised of oxide, doped oxide or low-temperature oxide;

said dielectric layer is comprised of a material selected from the group consisting of carbon doped oxide (SiCOH), carbon containing low K dielectric with a dielectric constant less than 3.0, spin on low-k dielectrics and CYD ultra-low-k.

9. The method of claim 1 wherein after the first etch step and before the second etch step, the first and second hardmask overhangs have a width between 3 and 15 nm;

the first interconnect opening has a diameter between 60 nm and 140 nm; and

after the second etch step, the first and second hardmask overhangs have a width between 0 and 30 angstroms.

10. The method of claim 1 wherein the first etch step comprises:

a Carbon-fluorine chemistry, a temperature between 20 and 100 degree C;

a pressure between 20 and 100 mTorr, a Radio-frequency power <

1000 w, with N₂, H₂, CO or/and Ar additives;

the first etch step has an etch selectivity between 1;

1 to 2;

1 of the dielectric layer to the first &

second hardmasks.

11. The method of claim 1 wherein the second etch comprise a wet dilute HF etch with a etch selectivity between the hardmask and the dielectric layer between 1:

1 and 2;

1.

12. The method of claim 1 wherein said first and said second hardmask are comprised of essentially the same material.

13. A method of fabrication of an interconnect opening for a semiconductor device;

comprising the steps of;

a) forming a lower interconnect and insulating layer over a semiconductor structure;

b) forming a first hardmask over said lower interconnect and insulating layer;

(1) said first hardmask is comprised of a material selected from the group consisting of;

oxide, doped oxide or low-temperature oxide;

c) forming a dielectric layer over said first hardmask layer;

(1) said dielectric layer is comprised of a material selected from the group consisting of;

SiCOH, carbon containing low K dielectric, spin on low-k dielectrics, porous silica glass, organo silica glass, aromatic hydrocarbon materials, and CVD ultra low-k dielectric;

d) forming a second hardmask over said dielectric layer;

(1) said second hardmask is comprised of a material selected from the group consisting of;

oxide, doped oxide or low-temperature oxide;

e) in a first etch step, etching a first interconnect opening in said first hardmask, dielectric layer and said second hardmask layer;

the first hardmask has an first hardmask overhang and the second hardmask has a second hardmask overhang where the first and second hardmask overhangs extend out past the sidewall of the dielectric layer;

the first etch forms a damaged dielectric layer from the dielectric layer lining the first interconnect opening;

(1) the first etch step comprises;

using a carbon-fluorine chemistry;

the first etch step has an etch selectivity between 1;

1 to 2;

1 of the dielectric layer to said first hardmask and said second hardmask;

f) in a second etch step, etching damaged dielectric layer and the overhangs of the hardmask layers to remove said first and second hardmask overhangs and form a first overhang-less interconnect opening and cleaning said first overhand-less interconnect opening;

(1) the second etch comprises an etch with an etch selectivity between the damaged dielectric layer and the hardmask between 1;

1 and 2;

1;

g) forming an interconnect in said first overhang-less interconnect opening.

14. The method of claim 13 wherein in the second etch step, the etch has an etch selectivity between the dielectric layer and said first hardmask and said second hardmask between about 1:

5 and 1;

100.

15. The method of claim 13 wherein in the first etch step, the first etch step comprises:

using a carbon-fluorine chemistry, at a temperature between 20 and 100 degree C;

at a pressure between 10 and 100 mTorr, at a radio-frequency power <

1000 w, with N₂, H₂, CO or/and Ar additives.

16. The method of claim 13 wherein the second etch comprise a wet dilute HF etch or a dry etch.

17. The method of claim 13 wherein said first and said second hardmasks are comprised of essentially the same material.

18. The method of claim 13 wherein said insulating layer is an interlevel dielectric layer and said lower interconnect is a contact to a substrate.

19. A method of forming a semiconductor device comprising:

providing a substrate prepared with a dielectric stack, the dielectric stack comprising a dielectric layer formed in between first and second dielectric hardmask layers; and

performing a first etch to form an opening through the first and second hardmask layers and the dielectric layer to expose sidewalls of the hardmask layers and dielectric layer, wherein sidewalls of the first and second hardmask layers extend beyond sidewalls of the dielectric layer to form first and second overhang regions by the first and second hardmask layers.

20. The method of claim 19 wherein the first and second hardmask layers comprise the same material.

21. The method of claim 19 wherein the first etch damages the sidewalls of the dielectric layer to form damaged portions lining the sidewalls of the dielectric layer.

22. The method of claim 21 wherein the damaged portions and hardmask layers have an etch selectivity of about 1:

1 to 2;

1 in a subsequent etch.

23. The method of claim 21 wherein

the sidewalls of the first and second hardmask layers are co-planar.

24. The method of claim 19, 20-22 or 23 further comprises performing a second etch, wherein the second etch produces sidewalls of the first and second hardmask layers which are coplanar with sidewalls of the dielectric layer.

25. The method of claim 24 wherein the second etch comprises a wet etch.

26. The method of claim 24 wherein the opening comprises an opening for an interconnect line and further comprises filling the opening to form the interconnect line.

27. A method of forming a semiconductor device comprising:

providing a substrate prepared with a dielectric stack, the dielectric stack comprising a dielectric layer formed in between first and second dielectric hardmask layers;

performing a first etch to form an interconnect line opening through the first and second hardmask layers and the dielectric layer to expose sidewalls of the hardmask layers and dielectric layer, wherein sidewalls of the dielectric layer are non-coplanar with sidewalls of the first and second hardmask layers in the interconnect line opening;

performing a second etch, wherein the second etch produces sidewalls of the first and second hardmask layers which are coplanar with sidewalls of the dielectric layer; and

forming an interconnect line in the interconnect line opening.

28. The method of claim 27 wherein the first and second hardmask layers comprise the same material.