In-plane switching mode liquid crystal display device

• US 7,602,465 B2
• Filed: 10/29/2003
• Issued: 10/13/2009
• Est. Priority Date: 10/31/2002
• Status: Expired due to Fees

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Young Wug, Kim, Kyong Seok
• Primary Examiner(s): Nelms; David
• Assistant Examiner(s): Chung; David Y
• Application Number:
  US10/695,396
• Publication Number:
  US 20040085503A1
• Time in Patent Office: 2,176 Days
• Field of Search: 349/38, 349/39, 349/141, 345 87-103
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

An In-Plane switching mode LCD device includes a plurality of gate and data lines crossing each other to define a plurality of pixel regions, a plurality of thin film transistor (TFT) formed at crossing points of the gate and data lines to be alternately positioned along lower and upper side pixel regions adjacent to corresponding gate lines, a plurality of storage lines disposed in an offset configuration to be parallel with the gate lines along the TFT regions, a plurality of pixel electrodes within the pixel regions to be connected to drain electrodes of the TFTs, and a plurality of common electrodes disposed at fixed intervals from the pixel electrodes to be connected to the storage lines.

Claims

1. An In-Plane switching mode LCD device, comprising:

a plurality of gate and data lines crossing each other to define a plurality of pixel regions;

a plurality of thin film transistors (TFTs) formed at crossing points of the gate and data lines to be alternately positioned along lower and upper side pixel regions adjacent to corresponding gate lines;

a plurality of storage lines to be parallel with the gate lines, each storage line being separated, wherein the storage line includes a first storage line parallel with the gate line along the TFTs, and a second storage line connected to the first storage line in parallel with the data line;

a plurality of pixel electrodes within the pixel regions to be connected to drain electrodes of the TFTs; and

a plurality of common electrodes disposed at fixed intervals from the pixel electrodes and connected to the storage lines,

wherein a high-level first common voltage and a low-level second common voltage are alternatively supplied to adjacent storage lines.

2. The device according to claim 1, wherein the first and second common voltages are inversely supplied to corresponding storage lines when a frame is changed.

3. The device according to claim 1, wherein the high-level first common voltage and the low-level second common voltage are synchronized with a gate pulse applied to the gate line corresponding to the storage line.

4. The device according to claim 1, further comprising a dummy line disposed along the lowermost portion of the horizontal gate line or the uppermost portion of the horizontal gate line.

5. The device according to claim 1, wherein the drain electrode of the TFT overlaps the storage line to form a storage capacitor.

6. The device according to claim 1, wherein the storage line is formed along a circumferential portion of the pixel region to be parallel with one of an adjacent gate and data line.

7. The device according to claim 6, wherein the storage line is formed along a corresponding thin film transistor in parallel with the gate line to be elongated to adjacent pixel regions by crossing the data line along one side of the pixel region.

8. The device according to claim 1, wherein the common electrode at least partially overlaps with the storage line.

9. The device according to claim 8, wherein the common electrode overlaps with the storage line at the common electrode portion adjacent to the data line within the pixel region.

10. The device according to claim 1, wherein the second storage line overlaps with the common electrode along a right side of the pixel region, and the first storage line crosses a left-side data line of the pixel region.

11. The device according to claim 1, wherein the second storage line overlaps with the common electrode along the left side of the pixel region, and the first storage line crosses the right-side data line within the pixel region.

12. The device according to claim 1, wherein the storage line is formed on the same layer as the gate line.

13. The device according to claim 12, wherein the storage line is formed of the same material as the gate line.

14. The device according to claim 1, wherein the pixel electrode is formed in a center portion of the pixel region, and the common electrode is formed along a circumferential portion of the pixel region at a predetermined interval from the pixel electrode.

15. The device according to claim 1, wherein the pixel electrode is formed in parallel with the data line.

16. The device according to claim 1, further comprising a gate driver for alternately supplying first and second common voltages Vcom(+)/Vcom(−

) to odd- and even-numbered storage lines, and for supplying a gate driving voltage to the gate lines.

17. The device according to claim 16, wherein the gate driver includes:

a shift register receiving a Gate Start Pulse signal GSP, a Gate Shift Clock signal GSC, and a Left/Right select signal L/R from a processor for shifting the GSC signal and outputting the shifted GSC signal;

a level shifter receiving a Gate Output Enable signal GOE from the processor for sequentially shifting signal levels output from the shift register in response to the GOE signal, and outputting the shifted signal level; and

a buffer receiving a high level VGH, a low level VGL, and first and second common voltages Vcom(+)/Vcom(−

) from the processor,

wherein the buffer is synchronized with the signal output from the level shifter to output scanning signals to the gate lines and first and second common voltages to the storage lines.

18. The device according to claim 17, wherein the shift register receives the Left/Right select signal L/R from the processor to perform a both-side shifting function.

19. The device according to claim 17, wherein the buffer alternately supplies the high-level first common voltage and the low-level second common voltage to the storage line corresponding to the gate line when supplying the scanning signal to the gate line.

20. The device according to claim 16, wherein an output terminal of the gate driver further includes a storage line signal supply pin disposed between gate line signal supply pins for supplying the signals to the gate lines.

21. The device according to claim 20, wherein the output terminal of the gate driver further includes two pins for a dummy line at lowermost or uppermost portion of the gate line signal supply pins.

22. The device according to claim 1, further comprising:

a gate driver for sequentially scanning signals to the gate lines, and alternately supplying the low and high level common voltages to the storage lines; and

a source driver for supplying the data voltage for negative fields to the data line of the pixel to which the high level common voltage is supplied, and for supplying the data voltage for positive fields to the data line of the pixel to which the low level common voltage is supplied.

23. The device according to claim 22, wherein the positive field is a data voltage value being larger than value of the low level common voltage, and the negative field is a data voltage value being smaller than a data voltage value of the high level common voltage.

24. The device according to claim 22, wherein the source driver outputs the data voltage for one of the positive fields and the data voltage for one of the negative fields with a gamma standard voltage circuit established by an additional circuit.

25. The device according to claim 22, wherein the source driver includes:

a shift register receiving a Source Start Pulse signal SSP, a Source Shift Clock signal SSC, and a Left/Right select signal L/R from a processor and stores the signals according to respective addresses;

first and second latch parts receiving a Load signal from the processor to receive and store RGB Digital Data signals for even/odd modes in corresponding addresses;

a decoder DAC receiving gamma standard voltages according to one of the positive fields and the negative fields for changing digital signals stored in the first and second latch parts into analog signals; and

an output buffer outputting the respective signals of the decoder according to corresponding data lines.

26. The device according to claim 25, wherein the decoder receives the gamma standard voltages for the positive fields and the negative fields according to a Polarity Out Load (POL) level supplied from the processor.

27. The device according to claim 1, wherein the plurality of storage lines disposed in an offset configuration to be parallel with the gate lines along the TFTs.