Dynamic RAM storage techniques
First Claim
1. A memory cell, the memory cell comprising:
- an n-channel transistor having a gate coupled to a read word line and a drain coupled to a read bit line;
an inverter having an output coupled to a source of the n-channel transistor;
a p-channel transistor coupled between an input of the inverter and a write bit line, a gate of the p-channel transistor being coupled to a write word line; and
a pass gate having a gate directly connected to the source of the n-channel transistor and coupled to the output of the inverter such that a voltage stored on the inverter is operable to drive a gate voltage of the pass gate, wherein the voltage stored on the inverter comprises a data bit of the memory cell.
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Abstract
Dynamic RAM (DRAM) cells are provided. Data can be read from a DRAM cell without draining the stored charge stored in the cell. During a read cycle, current flows between a Read Bit line and a supply voltage, and charge is not drained directly from the DRAM storage node. Each DRAM cell has a small number of transistors. The DRAM cell can be used to store configuration data on a programmable integrated circuits (IC). Pass gates are used on programmable ICs to drive signals across the chip. Data stored in DRAM cells is provided directly to the pass gates at the full supply voltage to prevent signal degradation. A p-channel transistor eliminates all N-type junctions from the storage node reducing the collection of particles that may cause soft errors.
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Citations
28 Claims
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1. A memory cell, the memory cell comprising:
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an n-channel transistor having a gate coupled to a read word line and a drain coupled to a read bit line; an inverter having an output coupled to a source of the n-channel transistor; a p-channel transistor coupled between an input of the inverter and a write bit line, a gate of the p-channel transistor being coupled to a write word line; and a pass gate having a gate directly connected to the source of the n-channel transistor and coupled to the output of the inverter such that a voltage stored on the inverter is operable to drive a gate voltage of the pass gate, wherein the voltage stored on the inverter comprises a data bit of the memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a memory cell, the method comprising:
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applying a first voltage on a write word line to turn on a p-channel transistor within the memory cell, wherein the p-channel transistor is coupled between an input of an inverter and a write bit line; applying a second voltage on the write bit line coupled to a drain of the p-channel transistor to store a charge at the inverter; applying a third voltage on the write word line to turn off the p-channel transistor; applying a fourth voltage on a read word line to turn on a first n-channel transistor, the first n-channel transistor coupled in series with a second n-channel transistor; and driving a gate voltage of a pass gate using the charge stored on the inverter. - View Dependent Claims (14, 15, 16, 17)
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18. A memory cell, the memory cell comprising:
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an n-channel transistor having a gate coupled to a read word line and a drain coupled to a read bit line; a single inverter having an output directly connected to a source of the n-channel transistor, such that a voltage stored on the inverter is operable as a data bit of the memory cell; and a p-channel transistor coupled between an input of the single inverter and a write bit line, a gate of the p-channel transistor being coupled to a write word line. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification