Method and apparatus for automatic configuration of multiple on-chip interconnects

• US 7,603,441 B2
• Filed: 12/27/2002
• Issued: 10/13/2009
• Est. Priority Date: 12/27/2002
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Chou, Chien-Chun, Synek, Kamil, Weber, Wolf-Dietrich
• Primary Examiner(s): Etienne; Ario
• Assistant Examiner(s): GOLD, AVI M
• Application Number:
  US10/330,591
• Publication Number:
  US 20040128341A1
• Time in Patent Office: 2,482 Days
• Field of Search: 709220-222, 710/306, 370/401, 370/402
• US Class Current: 709/220
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A method and apparatus for automatic configuration of multiple on-chip interconnects have been described. In one embodiment, the invention reduces the configuration time of several on-chip network features, and also ensures that these features are configured correctly to minimize errors in a design.

Claims

1. A method comprising:

an automatic configuration of a plurality of on-chip interconnects of an on-chip network, including,

determining a topology of the on-chip network wherein the determined topology is a directed acyclic graph tree or a fully connected graph;

configuring a plurality of bridge agents and core agents in the on-chip interconnects to communicate with each other based on said topology by configuring each of the plurality of on-chip interconnects with an address region that covers a region in system address space that encompasses the address regions of all core agents that are connected to the on-chip interconnect, where a first bridge agent is configured to communicate from a first on-chip interconnect to a second on-chip interconnect;

configuring a system address map of said network, wherein the first bridge agent and the core agents have address matching components inside the agent and check a correctness of an address by matching the address to the system address map; and

configuring a plurality of signals communicated between components in the on-chip network.

2. The method of claim 1 wherein said plurality of signals are selected from the group consisting of flag signals, error signals, and reset signals.

3. The method of claim 1 wherein one or more of said plurality of bridge agents are operating at different frequencies.

4. The method of claim 1 wherein the configuring each of the interconnects comprises:

configuring an address matcher of the first bridge agent associated with the first on-chip interconnect.

5. The method of claim 1 wherein the first on-chip interconnect is not connected to any cores and then a designer of the on-chip network connects a new core to the first interconnect via the first bridge agent of the first on-chip interconnect, and then the software process automatically configures an address matcher of the first bridge agent with an address region for accessing the new core.

6. A machine-readable medium having stored thereon instructions, which when executed by a machine to perform the method of claim 1.

7. A method comprising:

determining a plurality of address maps for a plurality of networks on a chip;

determining a network topology for said chip and said plurality of networks as being a directed acyclic graph tree or a fully connected graph;

configuring a system address map of said network, wherein bridge and core agents have address matching components inside the agents and check a correctness of an address by matching the address to the system address map; and

configuring a plurality of bridge agents and core agents in a plurality of on-chip interconnects in said chip to communicate with each other, by configuring each of the plurality of on-chip interconnects with an address region that covers a region in system address space that encompasses the address regions of all core agents that are connected to the on-chip interconnect.

13. A machine-readable medium having stored thereon instructions, which when executed by a machine to perform the method of claim 7.

14. A processing system comprising a processor coupled to a memory, said memory storing a set of instructions, which when executed said set of instructions performing the method of claim 7.

8. The method of 7 wherein said bridge agents each has a configuration feature selected from the group consisting of bridge forwarding, component identification, connection identifier support, error handling, interrupt handling, software generated reset, and timeout of requests.

9. The method of 7 wherein said bridge agents each has an interface feature selected from the group consisting of address space extension, byte enable extension, burst extension, connection identifier extension, data handshake extension, thread extension, write response extension, flag extension, error extension, control extension, and status extension.

10. The method of 7 wherein an address map of a specific one of said plurality of bridge agents includes an address map of a network to which said specific bridge agent is attached and an address map to all other attached networks.

11. The method of 10 wherein one or more of said plurality of bridge agents directly connected to each other have mutually exclusive address regions.

12. The method of 10 wherein said plurality of core agents have address regions that do not overlap.

15. A method for configuring on-chip network connections, the method comprising:

configuring one or more bridge agents and core agents in a plurality of on-chip interconnects of an on-chip network to communicate with each other over the interconnects based upon said on-chip network'"'"'s topology being a fully connected graph or a directed acyclic graph tree;

configuring and routing flag signals on a per core basis for one or more cores between components in the on-chip network;

configuring and routing error signals on a per core basis for one or more cores between components in the on-chip network;

configuring said one or more bridge agents with respective address matchers with an address region that covers a region in system address space that encompasses address regions of all core agents that are connected to the on-chip interconnect of which the one or more bridge agents are a part; and

configuring and routing reset signals between components in the on-chip network.

16. The method of claim 15 further comprising differing dock frequencies for entities selected from the group consisting of said one or more bridge agents, one or more micro-networks, and said one or more cores.

17. The method of claim 15 wherein a system address map encompasses all address regions of all said one or more bridge agents in possible communication with each other on said on-chip network.

18. The method of claim 15 further comprising:

taking into account that a specific one or more bridge agents'"'"' register resides in a same address space as a first bridge agent of the one or more bridge agents'"'"' on-chip interconnect.

19. The method of claim 15 wherein said one or more bridge agents that are not in a acyclic path tree of said network'"'"'s topology do not forward said error signals.

20. The method of claim 15 further comprising wherein any said reset signals routed to said one or more bridge agents are configured such that a specific micro-network, associated with a first bridge agent of the one or more bridge agents, that comes out of a reset last drives a reset across a connecting agent bridge.

21. The method of claim 15 wherein address matchers for said one or more bridge agents that directly connect two on-chip networks match mutually exclusive address regions.

22. The method of claim 15 wherein for any network topology address matchers of any two core agents do not overlap.

23. The method of claim 15 wherein if a first bridge agent of the one of said one or more bridge agents (A) does not bridge a first error signal of the one of said error signals (E) then a second bridge agent of the one or more bridge agents (B) connected to the first bridge agent (A) also does not bridge said first error signal of the one or more error signals (E).

24. A machine-readable medium having stored thereon instructions, which when executed by a machine to perform the method of claim 15.

25. A processing system comprising a processor coupled to a memory, said memory storing a set of instructions, which when executed said set of instructions performing the method of claim 15.

26. An apparatus comprising:

a processor that executes instructions; and

a memory device that stores said instructions, said instructions comprising;

means for automatic configuration of a plurality of on-chip interconnects of an on-chip network, including,

means for determining a topology of the on-chip network as being a fully connected graph or a directed acyclic graph;

means for configuring a plurality of bridge agents and core agents in the on-chip interconnects to communicate with each other based on said topology by configuring each of the plurality of on-chip interconnects with an address region that covers a region in system address space that encompasses the address regions of all core agents that are connected to the on-chip interconnect; and

means for configuring routing of a reset signal between interconnects, from one of the plurality of bridge agents in the on-chip network to another one of the bridge agents.

27. The apparatus of claim 26 further comprising:

means for checking said configuration of the routing of the reset signal.