Approach for managing interrupt load distribution

• US 7,610,425 B2
• Filed: 08/03/2006
• Issued: 10/27/2009
• Est. Priority Date: 08/22/2005
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Tripathi, Sunay, Solomita, Ethan
• Primary Examiner(s): Cleary; Thomas J
• Application Number:
  US11/499,027
• Publication Number:
  US 20070043970A1
• Time in Patent Office: 1,181 Days
• Field of Search: 710/48, 710/260, 710/264, 710/266, 710267-269, 718/102, 718/105
• US Class Current: 710/260
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3433 for load management allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 2209/508 Monitor
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system

Abstract

A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the processors that results from an initial mapping of the interrupts to the processors. The interrupt daemon determines whether there is a sufficient imbalance of the interrupts among the processors. If so, the interrupt daemon triggers a reassignment routine that generates a new mapping of the interrupts among the processors, and if not, the interrupt daemon goes to sleep for a specified time period. If the new mapping produces a sufficient improvement in the distribution of interrupts among the processors, based on the same criteria used to detect the imbalance, the new mapping is used by the central hub for subsequent distribution of interrupts to the processors. However, if the new mapping does not provide a sufficient improvement, the original mapping continues to be used.

Claims

1. A method for managing interrupt load distribution in a system comprising a plurality of processors, the method comprising:

monitoring a load of a device operatively connected to the plurality of processors;

determining a mapping for the device that specifies at least two interrupt channels mapped to at least two of the plurality of processors;

determining that a number of interrupt channels supported by the device is less than the number of interrupt channels specified in the mapping;

in response to determining that the number of interrupt channels supported by the device is less than the number of interrupt channels specified in the mapping;

designating a particular processor of the plurality of processors as a managing processor to receive interrupts on a particular interrupt channel, wherein the particular interrupt channel is used by the device to send interrupts;

receiving, by the managing processor, interrupts from the device on the particular interrupt channel; and

distributing, by the managing processor, the interrupts to the other processors of the plurality of processors.

2. The method of claim 1, wherein the device sends interrupts using only the particular interrupt channel, and wherein the method further comprises:

designating the particular interrupt channel as a managed interrupt channel.

3. The method of claim 1, wherein distributing by the managing processor the interrupts to the other processors of the plurality of processors comprises only sending the interrupts to a set of processors identified in the mapping.

4. The method of claim 3, wherein at least one processor in the set of processors handles interrupts from only the device.

5. The method of claim 3, wherein a user designates at least one processor in the set of processors as reserved to handle interrupts from only the device.

6. The method of claim 1, wherein at least one of the interrupts comprises a plurality of tasks, and wherein the plurality of tasks are distributed among the other processors of the plurality of processors.

7. The method of claim 6, wherein distributing the plurality of tasks among the other processors of the plurality of processors comprises:

determining that a particular task in the plurality of tasks is associated with a particular task category, wherein a task category identifies one or more tasks having common characteristics; and

based upon the particular task category for the particular task, assigning the particular task to a certain processor of the plurality of processors.

8. The method of claim 1, wherein the device is a network interface.

9. A machine-readable storage medium comprising a set of instructions which when executed by a machine, causes the machine to perform the following operations:

monitoring a load of a device operatively connected to a plurality of processors in the machine;

determining a mapping for the device that specifies at least two interrupt channels mapped to at least two of the plurality of processors;

determining that a number of interrupt channels supported by the device is less than the number of interrupt channels specified in the mapping;

in response to determining that the number of interrupt channels supported by the device is less than the number of interrupt channels specified in the mapping;

designating a particular processor of the plurality of processors as a managing processor to receive interrupts on a particular interrupt channel, wherein the particular interrupt channel is used by the device to send interrupts;

receiving, by the managing processor, interrupts from the device on the particular interrupt channel; and

distributing, by the managing processor, the interrupts to the other processors of the plurality of processors.

10. The machine-readable storage medium of claim 9, wherein the device sends interrupts using only the particular interrupt channel, and wherein the set of instructions cause the one or more processors to further perform on operations of:

designating the particular interrupt channel as a managed interrupt channel.

11. The machine-readable storage medium of claim 9, wherein distributing, by the managing processor, the interrupts to the other processors of the plurality of processors comprises only sending the interrupts to a set of processors identified in the mapping.

12. The machine-readable storage medium of claim 11, wherein at least one processor in the set of processors handles interrupts from only the device.

13. The machine-readable storage medium of claim 11, wherein a user designates at least one processor in the set of processors as reserved to handle interrupts from only the device.

14. The machine-readable storage medium of claim 9, wherein at least one of the interrupts comprises a plurality of tasks, and wherein the plurality of tasks are distributed among the other processors of the plurality of processors.

15. The machine-readable storage medium of claim 14, wherein distributing the plurality of tasks among the other processors of the plurality of processors comprises:

determining that a particular task in the plurality of tasks is associated with a particular task category, wherein a task category identifies one or more tasks having common characteristics; and

based upon the particular task category for the particular task, assigning the particular task to a certain processor of the plurality of processors.

16. The machine-readable storage medium of claim 9, wherein the device is a network interface.