Digitallysynthesized loop filter method and circuit particularly useful for a phase locked loop
First Claim
1. A method for controlling an oscillator in a phase locked loop system, said method comprising:
 generating a digital representation of a phase error signal of the phase locked loop system;
generating a multibit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and
generating an oscillator control signal corresponding to the accumulated digital phase error signal,wherein the digital phase error signal comprises a quantizedtime and quantizedvalue signal which encodes polarity of phase error.
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Abstract
In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In some embodiments, an analog phase detector is utilized whose phase error output signal is deltasigma modulated to encode the magnitude of the phase error using a digital (i.e., discretetime and discretevalue) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feedforward signal, and then conveyed as a control voltage to the voltagecontrolled oscillator. The equivalent “size” of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block.
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20 Claims

1. A method for controlling an oscillator in a phase locked loop system, said method comprising:

generating a digital representation of a phase error signal of the phase locked loop system; generating a multibit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and generating an oscillator control signal corresponding to the accumulated digital phase error signal, wherein the digital phase error signal comprises a quantizedtime and quantizedvalue signal which encodes polarity of phase error.  View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)


17. A method for controlling an oscillator in a phase locked loop system, said method comprising:

generating a digital representation of a phase error signal of the phase locked loop system; generating a multibit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and generating an oscillator control signal corresponding to the accumulated digital phase error signal, wherein the digital phase error signal comprises a quantizedtime and quantizedvalue signal which linearly encodes phase error.


18. A method for controlling an oscillator in a phase locked loop system, said method comprising:

generating a digital representation of a phase error signal of the phase locked loop system; generating a multibit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and generating an oscillator control signal corresponding to the accumulated digital phase error signal, wherein the multibit accumulated digital phase error signal is computed to a greater number of bits than that to which the oscillator control signal corresponds.


19. A method for controlling an oscillator in a phase locked loop system, said method comprising:

generating a digital representation of a phase error signal of the phase locked loop system; generating a multibit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and generating an oscillator control signal corresponding to the accumulated digital phase error signal, wherein the method is implemented entirely within an integrated circuit which is configured to recover clock and data from an incoming data signal having more than one possible data rate, said method further comprising varying the number of bits in the accumulated digital phase error signal based upon the data rate of the incoming data input signal.  View Dependent Claims (20)

1 Specification