Monolithic GPS RF front end integrated circuit
First Claim
1. A Global Positioning System (GPS) receiver, comprising:
- a Radio Frequency (RF) Front End, comprising;
a single stage downconverter using dual mixers that downconverts a received GPS signal;
an I/Q Intermediate Frequency (IF) active filter, coupled to the downconverter;
an Automatic Gain Control (AGC) amplifier, coupled to the downconverter;
an Analog-to-Digital Converter (ADC) coupled to the AGC amplifier; and
a frequency synthesizer section including an integrated Voltage Controlled Oscillator and a reference oscillator with a frequency of 24.5535 MHz plus or minus 40 parts per million (ppm), and further comprising;
a frequency doubler coupled to the reference oscillator;
a divide-by-9 circuit coupled to the frequency doubler;
a phase and frequency detector (PFD) coupled to the divide-by-9 circuit;
a charge pump coupled between the PFD and the VCO;
the voltage controller oscillator (VCO) that is also coupled to the downconverter;
a divide-by-41 circuit coupled to the VCO; and
a divide-by-7 circuit coupled between the divide-by-41 circuit and the PFD to make a phase locked loop; and
a digital processing section, coupled to the RF Front End, wherein the noise bandwidth of the GPS receiver is set by the IF active filter.
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Accused Products
Abstract
A highly integrated GPS RF Front End, an interface thereto, and a GPS receiver that incorporates the GPS RF front end, which uses a single conversion stage employing an image rejection mixer stage to eliminate the need for an image reject RF bandpass filter. Also a relatively high sample rate A/D is employed which allows a timeless monolithic IF Filter to be used. The disclosure also discusses a GPS Front End topology that is easily integrated from industry standard building blocks. With the broad variation in potential receiver designs, the present invention includes some specific receiver topologies that lend themselves to a high level of integration. The specific designs presented here are comprised of industry standard building blocks and functions that have been described elsewhere in the related art.
161 Citations
12 Claims
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1. A Global Positioning System (GPS) receiver, comprising:
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a Radio Frequency (RF) Front End, comprising; a single stage downconverter using dual mixers that downconverts a received GPS signal; an I/Q Intermediate Frequency (IF) active filter, coupled to the downconverter; an Automatic Gain Control (AGC) amplifier, coupled to the downconverter; an Analog-to-Digital Converter (ADC) coupled to the AGC amplifier; and a frequency synthesizer section including an integrated Voltage Controlled Oscillator and a reference oscillator with a frequency of 24.5535 MHz plus or minus 40 parts per million (ppm), and further comprising; a frequency doubler coupled to the reference oscillator; a divide-by-9 circuit coupled to the frequency doubler; a phase and frequency detector (PFD) coupled to the divide-by-9 circuit; a charge pump coupled between the PFD and the VCO; the voltage controller oscillator (VCO) that is also coupled to the downconverter; a divide-by-41 circuit coupled to the VCO; and a divide-by-7 circuit coupled between the divide-by-41 circuit and the PFD to make a phase locked loop; and a digital processing section, coupled to the RF Front End, wherein the noise bandwidth of the GPS receiver is set by the IF active filter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification