DC balance compensation for AC-coupled circuits

• US 7,620,121 B1
• Filed: 12/09/2004
• Issued: 11/17/2009
• Est. Priority Date: 12/09/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Tetzlaff, David E., Gaboury, Michael J.
• Primary Examiner(s): Liu; Shuwang
• Assistant Examiner(s): PATEL, DHAVAL V
• Application Number:
  US11/008,847
• Time in Patent Office: 1,804 Days
• Field of Search: 375/319
• US Class Current: 375/319
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance

Abstract

A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

Claims

1. A receiver comprising:

a first input port;

a second input port;

a first input capacitor;

a second input capacitor;

a differential amplifier having a first differential amplifier input coupled to the first input port through the first input capacitor and a second differential amplifier input coupled to the second input port through the second input capacitor;

a bias circuit switchably coupled to the first differential amplifier input and separately coupled to the second differential amplifier input and configured to provide a selected voltage to at least one of the first differential amplifier input and the second differential amplifier input;

a first switch disposed between the bias circuit and the first differential amplifier input; and

a data sensor configured to detect whether data is being received by the receiver disconnecting the bias circuit from the first differential amplifier input when the data is not being received by the receiver and re-connecting the bias circuit to the first differential amplifier input when data reception resumes.

2. The receiver of claim 1 wherein the bias circuit is a common mode bias circuit and the selected voltage is a common mode voltage applied to each of the first differential amplifier input and the second differential amplifier input.

3. The receiver of claim 1 wherein the data sensor is connected through a first impedance device to the first input port of the receiver and is connected through a second impedance device to the second input port of the receiver.

4. The receiver of claim 1 wherein the data sensor is connected through a first impedance device to the first differential amplifier input and is connected through a second impedance device to the second differential amplifier input.

5. The receiver of claim 1 wherein the data sensor is connected to an output of the differential amplifier.

6. The receiver of claim 1 further comprising a second switch disposed between the common mode bias circuit and the second differential amplifier input and coupled to the data sensor.