Method to reduce power in active shield circuits that use complementary traces

• US 7,622,944 B2
• Filed: 02/07/2008
• Issued: 11/24/2009
• Est. Priority Date: 12/26/2006
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Ziomek, Jason
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/027,494
• Publication Number:
  US 20080150574A1
• Time in Patent Office: 656 Days
• Field of Search: 326/8, 326/38, 326/56, 326 82- 86, 340/500, 340/568.2
• US Class Current: 326/8
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption

Abstract

The present invention provides a method and apparatus for securing an integrated circuit. A pair of conductive security traces are arranged on an integrated circuit. Driver means provide complementary HIGH and LOW voltage levels to a respective first end of each of the conductive security traces. A first switch means temporarily interrupts the driver means and isolates the pair of conductive security traces. A second switch means temporarily connects the first ends of the isolated pair of conductive security traces to each other so that both conductive traces are at the same voltage. The voltage at the first end of one of the security traces at the LOW voltage is then boosted to one-half of the HIGH voltage level (VDD/2) by the HIGH (VDD) voltage level at the first end of the other security trace. First and second comparators are provided, each of which compares voltages on their respective first ends of the pair of conductive security traces with voltages on a respective second end of the pair of conductive security traces. Means are provided for logically combining the output signals of the first and second comparators.

Claims

1. An integrated circuit, comprising:

a first security trace and a second security trace in the integrated circuit;

a driver to couple a first voltage level to a first end of the first security trace and a second voltage level to a first end of the second security trace, the first voltage level being different from the second voltage level; and

a first switch to selectively couple the driver to the first end of the first security trace and the first end of the second security trace.

2. The integrated circuit of claim 1, further comprising a second switch to couple the first security trace to the second security trace to permit charge to transfer between the first security trace and the second security trace.

3. The integrated circuit of claim 2, wherein the second switch comprises a bi-directional transmission gate.

4. The integrated circuit of claim 1, wherein the first security trace is conductive and has a first capacitance and the second security trace is conductive and has a second capacitance that is different from the first capacitance.

5. The integrated circuit of claim 1, further comprising:

a first comparator coupled to compare voltages on the first end and a second end of the first security trace;

a second comparator coupled to compare voltages on the first end and a second end of the second security trace; and

a logic circuit to combine output signals from the first comparator and the second comparator.

6. The integrated circuit of claim 1, wherein the first security trace and the second security trace are substantially parallel.

7. The integrated circuit of claim 1, wherein the driver and the first switch comprise tri-state drivers coupled to generate complementary output signals from a clock signal.

8. An integrated circuit comprising:

a first security trace and a second security trace that are part of the integrated circuit;

a first driver circuit to generate a first output signal to be coupled to a first end of the first security trace;

a second driver circuit to generate a second output signal to be coupled to a first end of the second security trace, the second output signal being different from the first output signal; and

a first switching circuit to couple the first security trace to the second security trace to permit charge transfer between the first security trace and the second security trace.

9. The integrated circuit of claim 8, wherein:

the first driver circuit is coupled to be driven by a clock signal and has an output terminal at which the first output signal is generated alternately at a HIGH voltage level and a LOW voltage level; and

the second driver circuit is coupled to be driven by the clock signal and has an output terminal at which the second output signal is generated to be a complement of the first output signal.

10. The integrated circuit of claim 8, further comprising a second switching circuit to decouple the first driver circuit from the first security trace and to decouple the second driver circuit from the second security trace.

11. The integrated circuit of claim 8, wherein the first switching circuit comprises a bi-directional transmission gate.

12. The integrated circuit of claim 8, wherein the first security trace is conductive and has a first capacitance and the second security trace is conductive and has a second capacitance that is different from the first capacitance.

13. The integrated circuit of claim 8, further comprising:

a first comparator coupled to compare voltages on the first end and a second end of the first security trace;

a second comparator coupled to compare voltages on the first end and a second end of the second security trace; and

a logic circuit coupled to combine output signals of the first comparator and the second comparator.

14. The integrated circuit of claim 8, wherein the first security trace and the second security trace are substantially parallel.

15. The integrated circuit of claim 10, wherein the first driver circuit, the second driver circuit and the second switching circuit comprise first and second tri-state drivers coupled to generate complementary output signals.

16. A method comprising:

coupling a first signal to a first end of a first security trace;

coupling a second signal to a first end of a second security trace, the second signal being different from the first signal; and

decoupling the first security trace from the first signal and decoupling the second security trace from the second signal.

17. The method of claim 16, further comprising coupling the first security trace to the second security trace to allow charge to transfer between the first security trace and the second security trace.

18. The method of claim 16, further comprising:

comparing voltages from the first end and a second end of the first security trace to generate a first output signal;

comparing voltages from the first end and a second end of the second security trace to generate a second output signal; and

logically combining the first output signal with the second output signal.

19. The method of claim 16, further comprising generating the first signal and the second signal from a clock signal wherein the second signal is at a HIGH voltage level and the first signal is at a LOW voltage level.

20. A method comprising:

coupling a first signal to a first end of a first security trace;

coupling a second signal to a first end of a second security trace, the second signal being different from the first signal; and

coupling the first security trace to the second security trace to allow charge to transfer between the first security trace and the second security trace.

21. The method of claim 20, further comprising decoupling the first security trace from the first signal and decoupling the second security trace from the second signal.

22. The method of claim 20, further comprising:

comparing voltages from the first end and a second end of the first security trace to generate a first output signal;

comparing voltages from the first end and a second end of the second security trace to generate a second output signal; and

logically combining the first output signal with the second output signal.

23. The method of claim 20, further comprising generating the first signal and the second signal from a clock signal wherein the second signal is at a HIGH voltage level and the first signal is at a LOW voltage level.