Serial output from a CMOS imager

• US 7,626,624 B2
• Filed: 10/08/2003
• Issued: 12/01/2009
• Est. Priority Date: 05/29/2001
• Status: Active Grant

• Current Assignee: Transchip Israel Limited
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Furman, Ben, Fraenkel, Miriam
• Primary Examiner(s): Hannett; James M
• Application Number:
  US10/474,701
• Publication Number:
  US 20050151868A1
• Time in Patent Office: 2,246 Days
• Field of Search: 348/308
• US Class Current: 348/308
• CPC Class Codes: H04N 11/20 Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 17/002 for television cameras
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 23/71 Circuitry for evaluating the brightness variation
• CPC Class Codes: H04N 23/73 by influencing the exposure time
• CPC Class Codes: H04N 23/745 Detection of flicker frequency or suppression of flicker wherein the flicker is caused by illumination, e.g. due to fluorescent tube illumination or pulsed LED illumination
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 5/16 Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
• CPC Class Codes: H04N 9/69 for modifying the colour signals by gamma correction controlling camera response for colour signals H04N23/83
• CPC Class Codes: H04N 9/73 Colour balance circuits, e.g. white balance circuits or colour temperature control camera processing pipelines for colour balance H04N23/88

Abstract

Systems, methods and devices related to detecting and transmitting images. Imaging systems and devices as well as methods of using such that are provided herein include flicker detection and/or correction; and/or built-in self test associated with various analog circuitry in the imaging devices; and/or power reduction ability; and/or pixels with charge evacuation functionality; and/or a parallel to serial conversion unit and associated serial output interface; and/or other advanced functionality.

Claims

1. A method for generating a serial output from a CMOS imager, the method comprising:

receiving an image derived from an image sensor;

converting the image to a serial data stream with a parallel to serial data conversion unit;

receiving a clock input signal from a source external to the CMOS imager;

generating an internal clock signal from the clock input signal; and

outputting a serial output signal, wherein the serial output signal comprises,

a clock output signal,

a data output signal, and

a qualifying output signal, the qualifying output signal indicating a presence of valid data on the data output signal,

wherein the serial output interface provides access to the serial data stream.

2. The method for generating a serial output from a CMOS imager of claim 1, wherein a division factor is applied to the clock input signal to produce the internal clock signal.

3. The method for generating a serial output from a CMOS imager of claim 1, wherein the frequency of the clock input signal comprises 64 MHz.

4. The method for generating a serial output from a CMOS imager of claim 1, further comprising receiving a control signal from a control unit which includes a programmable processor core.

5. The method for generating a serial output from a CMOS imager of claim 4, wherein the generating step further comprises generating the internal clock signal from the control signal.

6. The method for generating a serial output from a CMOS imager of claim 1, wherein the clock output signal is synchronized to the internal clock signal.

7. The method for generating a serial output from a CMOS imager of claim 1, wherein the data output signal comprises the serial data stream.

8. A CMOS imager, wherein the CMOS imager comprises:

a CMOS image sensor comprising a pixel array, wherein the sensor provides one or more image signals;

an analog to digital converter, wherein the analog to digital converter receives the one or more image signals and produces a digital image signal;

a translation unit, wherein the translation unit receives the digital image signal and provides color processing to produce a processed digital image signal which is output from the translation unit in a parallel mode;

a parallel to serial data conversion unit, wherein the parallel to serial data conversion unit receives the processed digital image signal and converts the image to a serial data stream;

an input interface;

a clock unit which produces an internal clock signal, the internal clock signal generated from a clock input signal which is received by the clock unit from a source external to the CMOS imager through the input interface; and

a serial output interface, outputting a serial output signal, the serial output signal including,

a clock output signal,

a data output signal, and

a qualifying output signal, the qualifying output signal indicating a presence of valid data on the data output signal,

wherein the serial output interface provides access to the serial data stream.

9. The CMOS imager of claim 8, further comprising a control unit which includes a programmable processor core and produces a control signal, wherein the internal clock signal is further generated from the control signal.

10. The CMOS imager of claim 8, wherein a division factor is applied to the clock input signal to produce the internal clock signal.

11. The CMOS imager of claim 8, wherein the serial output interface further outputs the clock output signal synchronized to the internal clock signal.

12. The CMOS imager of claim 8, wherein the CMOS image sensor, the analog to digital converter, and the translation unit comprise a single monolithic chip.

13. A CMOS imager comprising:

an image sensor;

a parallel to serial data conversion unit, wherein the parallel to serial data conversion unit receives an image derived from the image sensor and converts the image to a serial data stream; and

an input interface;

a clock unit which produces an internal clock signal, the internal clock signal generated from a clock input signal which is received by the clock unit from a source external to the CMOS imager through the input interface; and

a serial output interface, outputting a serial output signal including,

a clock output signal, and

a data output signal,

wherein the serial output interface provides access to the serial data stream, and the clock output signal is only active when valid data is presented on the data output signal.

14. A CMOS imager comprising:

an image sensor;

a parallel to serial data conversion unit, wherein the parallel to serial data conversion unit receives an image derived from the image sensor and converts the image to a serial data stream; and

an input interface;

a clock unit which produces an internal clock signal, the internal clock signal generated from a clock input signal which is received by the clock unit from a source external to the CMOS imager through the input interface; and

a serial output interface, outputting a serial output signal comprising,

a clock output signal, and

a data output signal,

wherein the serial output interface provides access to the serial data stream, the serial output signal further comprises a qualifying output signal, and the qualifying output signal indicates the presence of valid data on the data output signal.

15. The CMOS imager of claim 14, wherein the clock output signal is only active when valid data is presented on the data output signal.

16. The CMOS imager of claim 14, wherein a division factor is applied to the clock input signal to produce the internal clock signal.

17. The CMOS imager of claim 14, wherein the frequency of the clock input signal comprises 64 MHz.

18. The CMOS imager of claim 14, further comprising a control unit.

19. The CMOS imager of claim 14, wherein the clock output signal is synchronized to the internal clock signal.

20. The CMOS imager of claim 14, wherein the data output signal comprises the serial data stream.

21. The CMOS imager of claim 14, wherein the input interface and the serial output interface comprise the same connector.