Method for modulating stresses of a contact etch stop layer

• US 7,629,273 B2
• Filed: 09/19/2006
• Issued: 12/08/2009
• Est. Priority Date: 09/19/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Hung Chun, Lu, Yung-Cheng, Yu, Chen-Hua, Chang, Hui-Lin, Shen, Ting-Yu
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US11/523,674
• Publication Number:
  US 20080085607A1
• Time in Patent Office: 1,176 Days
• Field of Search: 438/758, 438/771, 438/775, 438/778, 438/798, 257/E21.241
• US Class Current: 438/792
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.

Claims

1. A method for forming a semiconductor structure, the method comprising:

providing a substrate comprising a first device region;

forming a first metal-oxide-semiconductor (MOS) device in the first device region;

forming a stressed layer over the first MOS device;

implanting the stressed layer; and

performing a post-treatment to modulate a stress of the stressed layer, wherein the post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing and combinations thereof.

2. The method of claim 1, wherein the stress of the stressed layer is modulated from one of compressive type or tensile type to an opposite type.

3. The method of claim 1, wherein the stress of the stressed layer is increased in magnitude after the step of performing the post-treatment.

4. The method of claim 1, wherein the substrate further comprises:

a second device region; and

an additional MOS device having an opposite type from the first MOS device, wherein the stressed layer is over the additional MOS device, and wherein the stressed layer in the second device region is masked by a mask layer during the step of performing the post-treatment.

5. The method of claim 4 further comprising:

masking the first device region; and

performing an additional post-treatment to the stressed layer in the second device region, wherein process conditions for the post-treatment are substantially different from the process conditions of the additional post-treatment.

6. The method of claim 1, wherein the stressed layer comprises a material selected from the group consisting essentially of carbon-doped silicon oxide, carbon-doped silicon nitride, silicon nitride, silicon oxynitride and combinations thereof.

7. A method for forming a semiconductor structure, the method comprising:

providing a substrate having a first active region and a second active region;

forming a first MOS device in the first active region;

forming a second MOS device having an opposite conductivity type than the first MOS device in the second active region;

forming a contact etch stop layer overlying the first and the second MOS devices;

forming a mask layer to mask the first MOS device;

performing an implantation in the contact etch stop layer; and

performing a curing process to modulate a stress of the contact etch stop layer over the second MOS device, wherein, after the curing process, the stress is of an opposite type than before the curing process, and wherein the curing process is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.

8. The method of claim 7, wherein the first MOS device is a PMOS device and the second MOS device is an NMOS device.

9. The method of claim 7 further comprising:

removing the mask layer;

forming an additional mask layer to mask the second MOS device; and

performing an additional curing process, wherein process conditions of the curing process and the additional curing process are substantially different.