Hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders

• US 7,633,829 B2
• Filed: 10/22/2007
• Issued: 12/15/2009
• Est. Priority Date: 12/30/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Fasoli, Luca G., So, Kenneth K.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US11/876,563
• Publication Number:
  US 20080101149A1
• Time in Patent Office: 785 Days
• Field of Search: 365/230.06, 365/230.03
• US Class Current: 365/230.06
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder circuits. The first hierarchical decoder circuit may include a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs, a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs, and a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.

Claims

1. A method comprising:

decoding address information and selecting one or more array lines of a first type in a memory array using a first hierarchical decoder circuit comprising at least two hierarchical levels of multi-headed decoder circuits;

wherein the decoding and selecting comprises

decoding a plurality of address signal inputs using a first-level decoder circuit, and generating a plurality of first-level decoded outputs thereof;

coupling each respective first-level decoded output to a respective one of a plurality of second-level multi-headed decoder circuits, each providing a respective plurality of second-level decoded outputs; and

coupling each respective second-level decoded output to a respective one of a plurality of third-level multi-headed decoder circuits, each providing a respective plurality of third-level decoded outputs coupled to the memory array.

2. The method as recited in claim 1 wherein the memory array comprises a three-dimensional memory array having at least two memory planes, said memory array comprising:

array lines of first and second types coupled to memory cells;

a respective plurality of array lines of the first type on each of at least one array line layer; and

a respective plurality of array lines of the second type on each of at least one array line layer.

3. The method as recited in claim 1 wherein each respective one of the second-level multi-headed decoder circuits comprises a respective plurality of second-level driver circuits, each second-level driver circuit comprising:

an input coupled to the respective one of the first-level decoded outputs; and

an output coupled to the corresponding one of the respective plurality of second-level decoded outputs;

each second-level driver circuit for coupling its output to an associated one of a plurality of first bias nodes at times when the first-level decoded output coupled to its input is selected, and otherwise for coupling its output to an associated one of a plurality of second bias nodes.

4. The method as recited in claim 3 wherein the first hierarchical decoder circuit further comprises:

a first plurality of second-level bias circuits for respectively generating a suitable condition on the plurality of first bias nodes; and

a second plurality of second-level bias circuits for respectively generating a suitable condition on the plurality of second bias nodes;

and wherein;

the suitable condition on at least one of the first bias nodes is at times a selected second-level decoded output bias condition; and

the suitable condition on at least another one of the first bias nodes is at times an unselected second-level decoded output bias condition.

5. The method as recited in claim 4 wherein the second-level driver circuits respectively comprise:

a first transistor circuit for coupling the output of the driver circuit to the associated one of the plurality of first bias nodes when the first-level decoded output coupled to the input is selected; and

a second transistor circuit for coupling the output of the driver circuit to the associated one of the plurality of second bias nodes when the first-level decoded output coupled to the input is unselected;

wherein the first transistor circuit comprises two parallel-connected transistor devices of opposite conductivity type.

6. The method as recited in claim 4 wherein the second-level driver circuits respectively comprise:

a first transistor circuit for coupling the output of the driver circuit to the associated one of the plurality of first bias nodes when the first-level decoded output coupled to the input is selected; and

a second transistor circuit for coupling the output of the driver circuit to the associated one of the plurality of second bias nodes when the first-level decoded output coupled to the input is unselected;

wherein the second transistor circuit comprises at least two parallel-connected transistor devices controlled by separate signals.

7. The method as recited in claim 3 wherein each respective one of the third-level multi-headed decoder circuits comprises a respective plurality of third-level driver circuits, each third-level driver circuit comprising:

an input coupled to the respective one of the second-level decoded outputs; and

an output coupled to the corresponding one of the respective plurality of third-level decoded outputs;

each third-level driver circuit for coupling its output to an associated one of a plurality of third bus lines at times when the second-level decoded output coupled to its input is selected, and otherwise for coupling its output to an associated one of a plurality of fourth bias nodes.

8. The method as recited in claim 7 wherein the first hierarchical decoder circuit further comprises:

a first plurality of third-level bias circuits for respectively generating at times a suitable condition on the plurality of third bus lines; and

a second plurality of third-level bias circuits for respectively generating a suitable condition on the plurality of fourth bias nodes;

wherein;

the suitable condition on at least one of the third bus lines is at times a selected third-level decoded output bias condition; and

the suitable condition on at least another one of the third bias nodes is at times an unselected third-level decoded output bias condition.

9. The method as recited in claim 8 wherein the third-level driver circuits respectively comprise:

a third transistor circuit for coupling the output of the third-level driver circuit to the associated one of the plurality of third bus lines when the second-level decoded output coupled to the input is selected; and

a fourth transistor circuit for coupling the output of the third-level driver circuit to the associated one of the plurality of fourth bias nodes when the second-level decoded output coupled to the input is unselected;

wherein at least one of the third transistor circuit and fourth transistor circuit comprises at least two parallel-connected transistor devices of opposite conductivity type and controlled by separate signals.

10. The method as recited in claim 1 wherein the second-level decoded outputs traverse across substantially the entire memory array.

11. The method as recited in claim 1 wherein the second-level decoded outputs are driven to a voltage above VDD for at least one of a selected and unselected bias condition.

12. The method as recited in claim 1 wherein:

the memory array comprises a three-dimensional array having at least two memory planes disposed above a substrate, and further having a respective plurality of array lines of the first type on at least one array line layer, and having a respective plurality of array lines of the second type on at least one array line layer; and

at least one plurality of the second-level and third-level multi-headed decoder circuits is disposed substantially within the lateral extent of the memory array.

13. The method as recited in claim 12 wherein the plurality of third-level multi-headed decoder circuits is disposed substantially outside the memory array.

14. The method as recited in claim 12 wherein:

the plurality of second-level multi-headed decoder circuits is disposed substantially outside the memory array;

the third-level decoded outputs comprise bit lines in the memory array, each coupled to an associated plurality of memory cells in the memory array; and

the plurality of third bus lines are respectively coupled to a respective read/write bus.

15. The method as recited in claim 12 wherein:

the plurality of second-level multi-headed decoder circuits are disposed substantially outside the memory array; and

the plurality of third-level multi-headed decoder circuits are disposed substantially beneath the memory array.

16. The method as recited in claim 3 wherein:

the plurality of second-level driver circuits within a second-level multi-headed decoder circuit is arranged in groups of such second-level driver circuits, individual second-level driver circuits within a group being respectively coupled to a respective one of the plurality of first bias lines, but together coupled to a respective one of the plurality of second bias lines shared by the group.

17. A method for making a product incorporating a memory array, said method comprising:

providing a memory array comprising array lines of first and second types coupled to memory cells;

providing a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type, said first hierarchical decoder circuit comprising at least two hierarchical levels of multi-headed decoder circuits;

wherein said providing a first hierarchical decoder circuit comprises

providing a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs;

providing a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs; and

providing a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.

18. The method as recited in claim 17 wherein the memory array comprises a three-dimensional memory array having at least two memory planes, said memory array comprising:

array lines of first and second types coupled to memory cells;

a respective plurality of array lines of the first type on each of at least one array line layer; and

a respective plurality of array lines of the second type on each of at least one array line layer.

19. The method as recited in claim 17 wherein each respective one of the second-level multi-headed decoder circuits comprises a respective plurality of second-level driver circuits, each second-level driver circuit comprising:

an input coupled to the respective one of the first-level decoded outputs; and

an output coupled to the corresponding one of the respective plurality of second-level decoded outputs;

each second-level driver circuit for coupling its output to an associated one of a plurality of first bias nodes at times when the first-level decoded output coupled to its input is selected, and otherwise for coupling its output to an associated one of a plurality of second bias nodes.

20. The method as recited in claim 19 wherein the first hierarchical decoder circuit further comprises:

a first plurality of second-level bias circuits for respectively generating a suitable condition on the plurality of first bias nodes; and

a second plurality of second-level bias circuits for respectively generating a suitable condition on the plurality of second bias nodes;

and wherein;

the suitable condition on at least one of the first bias nodes is at times a selected second-level decoded output bias condition; and

the suitable condition on at least another one of the first bias nodes is at times an unselected second-level decoded output bias condition.

21. The method as recited in claim 17 wherein the second-level decoded outputs traverse across substantially the entire memory array.

22. The method as recited in claim 17 wherein the second-level decoded outputs are driven to a voltage above VDD for at least one of a selected and unselected bias condition.

23. The method as recited in claim 17 wherein:

the memory array comprises a thee-dimensional array having at least two memory planes disposed above a substrate, and further having a respective plurality of array lines of the first type on at least one array line layer, and having a respective plurality of array lines of the second type on at least one array line layer; and

at least one plurality of the second-level and third-level multi-headed decoder circuits is disposed substantially within the lateral extent of the memory array.

24. The method as recited in claim 23 wherein:

the plurality of second-level multi-headed decoder circuits is disposed substantially outside the memory array;

the third-level decoded outputs comprise bit lines in the memory array, each coupled to an associated plurality of memory cells in the memory array; and

the plurality of third bus lines are respectively coupled to a respective read/write bus.

25. The method as recited in claim 23 wherein:

the plurality of second-level multi-headed decoder circuits are disposed substantially outside the memory array; and

the plurality of third-level multi-headed decoder circuits are disposed substantially beneath the memory array.

26. The method as recited in claim 19 wherein:

the plurality of second-level driver circuits within a second-level multi-headed decoder circuit is arranged in groups of such second-level driver circuits, individual second-level driver circuits within a group being respectively coupled to a respective one of the plurality of first bias lines, but together coupled to a respective one of the plurality of second bias lines shared by the group.