Resistive memory cells and devices having asymmetrical contacts

• US 7,639,521 B2
• Filed: 03/17/2006
• Issued: 12/29/2009
• Est. Priority Date: 03/28/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, In-Gyu, Kim, Dong-Chul, Lee, Moon-Sook
• Primary Examiner(s): Le; Vu A
• Assistant Examiner(s): Yang; Han
• Application Number:
  US11/378,945
• Publication Number:
  US 20060215445A1
• Time in Patent Office: 1,383 Days
• Field of Search: 365/158, 365/208, 365/174, 365/148, 365/163, 365/171, 365/173
• US Class Current: 365/148
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 2213/52 Structure characterized by the electrode material, shape, etc.
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Claims

1. A memory device comprising:

a plurality of first electrode lines arranged in parallel on a substrate;

a plurality of second electrode lines arranged in parallel on the substrate transverse to the first electrode lines;

a plurality of electrode plugs electrically coupled to the first electrode lines, respective ones of the electrode plugs disposed between ones of the first and second electrode lines at respective intersections thereof; and

a resistive thin film material region, the resistive thin film material region having a first surface directly in contact with at least one of the electrode plugs and a second surface directly in contact with at least one of the second electrode lines,

wherein the second surface has a greater area than the first surface and wherein a width of the resistive thin film material region is equal to or greater than a width of the at least one of the second electrode lines, and wherein the first electrode lines and the second electrode lines serve as word lines and bit lines, respectively, or wherein the first electrode lines and the second electrode lines serve as bit lines and word lines, respectively.

2. The memory device of claim 1, wherein the resistive thin film material region comprises a colossal magneto-resistive material.

3. The memory device of claim 1, wherein the resistive thin film material region comprises an insulating material with a perovskite phase and/or a transition metal oxide.

4. The memory device of claim 1, wherein an area of overlap between the at least one of the electrode plugs and the resistive thin film material region is smaller than an area of overlap between the resistive thin film material region and the at least one of the second electrode lines.

5. The memory device of claim 1, wherein a width of the resistive thin film material region is greater than a width of the at least one of the second electrode lines contacting the resistive thin film material region.

6. The memory device of claim 1, wherein the resistive thin film material region comprises an array of individual patterns disposed between ones of the first and second electrode lines at respective intersections thereof.

7. The memory device of claim 1, wherein the resistive thin film material region comprises a plurality of regions in a resistive thin-film material layer that overlaps multiple ones of the electrode plugs.

8. A memory device comprising:

a plurality of first conductive lines arranged in parallel on a substrate;

a plurality of second conductive lines arranged in parallel on the substrate transverse to the first conductive lines;

a plurality of electrode plugs electrically coupled to the first conductive lines, respective ones of the electrode plugs disposed between ones of the first and second conductive lines at respective intersections thereof; and

a resistive material layer between one of the electrode plugs and one of the second conductive lines and directly in contact with each of the one of the electrode plugs and the one of the second conductive lines, wherein the resistive material layer and the one of the second conductive lines cover the one of the electrode plugs and extend outwardly from the one of the electrode plugs and wherein a width of the resistive material layer is equal to or greater than a width of the one of the second conductive lines, and wherein the first conductive lines and the second conductive lines serve as word lines and bit lines, respectively, or wherein the first conductive lines and the second conductive lines serve as bit lines and word lines, respectively.

9. The memory device of claim 8, wherein the resistive material layer comprises a colossal magneto-resistive material.

10. The memory device of claim 8, wherein the resistive material layer comprises an insulating material with a perovskite phase and/or a transition metal oxide.

11. The memory device of claim 8, wherein the resistive material layer comprises an array of individual patterns disposed between ones of the first and second conductive lines at respective intersections thereof.

12. The memory device of claim 8, wherein the resistive material layer overlaps multiple ones of the electrode plugs and multiple ones of the second conductive lines.